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XC9572XL High Performance
CPLD
DS057 (v1.1) August 28, 2000 |
Preliminary Product Specification |
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Features
•5 ns pin-to-pin logic delays
•System frequency up to 178 MHz
•72 macrocells with 1,600 usable gates
•Available in small footprint packages
-44-pin PLCC (34 user I/O pins)
-44-pin VQFP (34 user I/O pins)
-48-pin CSP (38 user I/O pins)
-64-pin VQFP (52 user I/O pins)
-100-pin TQFP (72 user I/O pins)
•Optimized for high-performance 3.3V systems
-Low power operation
-5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals
-3.3V or 2.5V output capability
-Advanced 0.35 micron feature size CMOS FastFLASH™ technology
•Advanced system features
-In-system programmable
-Superior pin-locking and routability with FastCONNECT II™ switch matrix
-Extra wide 54-input Function Blocks
-Up to 90 product-terms per macrocell with individual product-term allocation
-Local clock inversion with three global and one product-term clocks
-Individual output enable per output pin
-Input hysteresis on all user and boundary-scan pin inputs
-Bus-hold circuitry on all user pin inputs
-Full IEEE Standard 1149.1 boundary-scan (JTAG)
•Fast concurrent programming
•Slew rate control on individual outputs
•Enhanced data security features
•Excellent quality and reliability
-Endurance exceeding 10,000 program/erase cycles
-20 year data retention
-ESD protection exceeding 2,000V
•Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package
Description
cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be used:
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
Where:
MCHP = Macrocells in high-performance (default) mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation.
Figure 1 shows the above estimation in a graphical form.
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100 |
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178 MHz |
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80 |
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(mA) |
60 |
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Performance |
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104 MHz |
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High |
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CC |
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40 |
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Power |
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Typical |
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Low |
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20 |
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0 |
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50 |
100 |
150 |
200 |
The XC9572XL is a 3.3V CPLD targeted for high-perfor- |
Clock Frequency (MHz) |
DS057_01_081500 |
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mance, low-voltage applications in leading-edge communi- |
Figure 1: Typical ICC vs. Frequency for XC9572XL |
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS057 (v1.1) August 28, 2000 |
www.xilinx.com |
1 |
Preliminary Product Specification |
1-800-255-7778 |
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XC9572XL High Performance CPLD
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JTAG Port |
1 |
JTAG |
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In-System Programming Controller |
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Controller |
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54 |
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18 |
Function |
I/O |
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Block 1 |
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I/O |
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Macrocells |
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1 to 18 |
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I/O |
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Matrix |
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18 |
Block 2 |
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I/O |
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54 |
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Function |
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SwitchII |
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Blocks |
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Macrocells |
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I/O |
FastCONNECT |
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1 to 18 |
I/O |
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1 to 18 |
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54 |
I/O |
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18 |
Function |
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Block 3 |
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I/O |
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Macrocells |
I/O |
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3 |
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I/O/GCK |
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54 |
1 |
18 |
Function |
I/O/GSR |
Block 4 |
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Macrocells |
I/O/GTS |
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1 to 18 |
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DS057_02_082800 |
Figure 2: XC9572XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2 |
www.xilinx.com |
DS057 (v1.1) August 28, 2000 |
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1-800-255-7778 |
Preliminary Product Specification |
R
XC9572XL High Performance CPLD
Absolute Maximum Ratings
Symbol |
Description |
Value |
Units |
VCC |
Supply voltage relative to GND |
–0.5 to 4.0 |
V |
VIN |
Input voltage relative to GND(1) |
–0.5 to 5.5 |
V |
V |
Voltage applied to 3-state output(1) |
–0.5 to 5.5 |
V |
TS |
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T |
Storage temperature (ambient) |
–65 to +150 |
oC |
STG |
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T |
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) |
+260 |
oC |
SOL |
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T |
Junction temperature |
+150 |
oC |
J |
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Notes: |
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1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this overor undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
2.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol |
Parameter |
Min |
Max |
Units |
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V |
CCINT |
Supply voltage for internal logic |
Commercial T = 0oC to 70oC |
3.0 |
3.6 |
V |
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and input buffers |
A |
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Industrial T = –40oC to +85oC |
3.0 |
3.6 |
V |
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A |
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VCCIO |
Supply voltage for output drivers for 3.3V operation |
3.0 |
3.6 |
V |
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Supply voltage for output drivers for 2.5V operation |
2.3 |
2.7 |
V |
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VIL |
Low-level input voltage |
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0 |
0.80 |
V |
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VIH |
High-level input voltage |
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2.0 |
5.5 |
V |
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VO |
Output voltage |
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0 |
VCCIO |
V |
Quality and Reliability Characteristics
Symbol |
Parameter |
Min |
Max |
Units |
TDR |
Data Retention |
20 |
- |
Years |
NPE |
Program/Erase Cycles (Endurance) |
10,000 |
- |
Cycles |
VESD |
Electrostatic Discharge (ESD) |
2,000 |
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Volts |
DC Characteristic Over Recommended Operating Conditions
Symbol |
Parameter |
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Test Conditions |
Min |
Max |
Units |
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VOH |
Output high voltage for 3.3V outputs |
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IOH = –4.0 mA |
2.4 |
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V |
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Output high voltage for 2.5V outputs |
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IOH = –500 A |
90% VCCIO |
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V |
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VOL |
Output low voltage for 3.3V outputs |
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IOL = 8.0 mA |
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0.4 |
V |
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Output low voltage for 2.5V outputs |
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IOL = 500 A |
- |
0.4 |
V |
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IIL |
Input leakage current |
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VCC = Max |
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±10 |
A |
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VIN = GND or VCC |
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IIH |
I/O high-Z leakage current |
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VCC = Max |
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±10 |
A |
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VIN = GND or VCC |
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CIN |
I/O capacitance |
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VIN = GND |
- |
10 |
pF |
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f = 1.0 MHz |
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ICC |
Operating supply current |
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VI = GND, No load |
20 (Typical) |
mA |
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(low power mode, active) |
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f = 1.0 MHz |
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DS057 (v1.1) August 28, 2000 |
www.xilinx.com |
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3 |
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Preliminary Product Specification |
1-800-255-7778 |
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