XILINX XC9572XL-7VQ64I, XC9572XL-7VQ64C, XC9572XL-7VQ44I, XC9572XL-7VQ44C, XC9572XL-7TQ100I Datasheet

...
0 (0)

R

XC9572XL High Performance

CPLD

DS057 (v1.1) August 28, 2000

Preliminary Product Specification

 

 

Features

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

72 macrocells with 1,600 usable gates

Available in small footprint packages

-44-pin PLCC (34 user I/O pins)

-44-pin VQFP (34 user I/O pins)

-48-pin CSP (38 user I/O pins)

-64-pin VQFP (52 user I/O pins)

-100-pin TQFP (72 user I/O pins)

Optimized for high-performance 3.3V systems

-Low power operation

-5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals

-3.3V or 2.5V output capability

-Advanced 0.35 micron feature size CMOS FastFLASH™ technology

Advanced system features

-In-system programmable

-Superior pin-locking and routability with FastCONNECT II™ switch matrix

-Extra wide 54-input Function Blocks

-Up to 90 product-terms per macrocell with individual product-term allocation

-Local clock inversion with three global and one product-term clocks

-Individual output enable per output pin

-Input hysteresis on all user and boundary-scan pin inputs

-Bus-hold circuitry on all user pin inputs

-Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

-Endurance exceeding 10,000 program/erase cycles

-20 year data retention

-ESD protection exceeding 2,000V

Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package

Description

cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview.

Power Estimation

Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.

For a general estimate of ICC, the following equation may be used:

ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f

Where:

MCHP = Macrocells in high-performance (default) mode

MCLP = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation.

Figure 1 shows the above estimation in a graphical form.

 

100

 

 

 

 

178 MHz

 

 

 

 

 

 

 

 

 

80

 

 

 

 

 

 

(mA)

60

 

 

Performance

 

104 MHz

 

 

 

 

 

 

 

High

 

 

 

 

 

 

 

 

CC

 

 

 

 

 

40

 

 

 

 

 

 

I

 

Power

 

 

 

Typical

 

Low

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

50

100

150

200

The XC9572XL is a 3.3V CPLD targeted for high-perfor-

Clock Frequency (MHz)

DS057_01_081500

mance, low-voltage applications in leading-edge communi-

Figure 1: Typical ICC vs. Frequency for XC9572XL

© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS057 (v1.1) August 28, 2000

www.xilinx.com

1

Preliminary Product Specification

1-800-255-7778

 

XILINX XC9572XL-7VQ64I, XC9572XL-7VQ64C, XC9572XL-7VQ44I, XC9572XL-7VQ44C, XC9572XL-7TQ100I Datasheet

XC9572XL High Performance CPLD

R

 

 

3

 

 

 

JTAG Port

1

JTAG

 

In-System Programming Controller

Controller

 

 

 

 

 

 

 

 

 

 

 

54

 

 

 

 

18

Function

I/O

 

 

 

Block 1

I/O

 

 

 

 

Macrocells

 

 

 

 

1 to 18

I/O

 

 

Matrix

 

 

 

 

 

18

Block 2

I/O

 

 

 

 

54

 

 

 

 

Function

 

 

 

SwitchII

 

 

 

Blocks

 

Macrocells

 

 

 

 

 

 

 

I/O

FastCONNECT

 

1 to 18

I/O

 

 

 

1 to 18

 

 

 

 

 

54

I/O

 

 

 

18

Function

 

 

 

 

Block 3

I/O

 

 

 

 

Macrocells

I/O

 

 

 

 

 

3

 

 

I/O/GCK

 

54

1

18

Function

I/O/GSR

Block 4

2

 

Macrocells

I/O/GTS

 

1 to 18

 

 

 

 

DS057_02_082800

Figure 2: XC9572XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

2

www.xilinx.com

DS057 (v1.1) August 28, 2000

 

1-800-255-7778

Preliminary Product Specification

R

XC9572XL High Performance CPLD

Absolute Maximum Ratings

Symbol

Description

Value

Units

VCC

Supply voltage relative to GND

–0.5 to 4.0

V

VIN

Input voltage relative to GND(1)

–0.5 to 5.5

V

V

Voltage applied to 3-state output(1)

–0.5 to 5.5

V

TS

 

 

 

T

Storage temperature (ambient)

–65 to +150

oC

STG

 

 

 

T

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

+260

oC

SOL

 

 

 

T

Junction temperature

+150

oC

J

 

 

 

Notes:

 

 

 

1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this overor undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

2.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

Max

Units

V

CCINT

Supply voltage for internal logic

Commercial T = 0oC to 70oC

3.0

3.6

V

 

and input buffers

A

 

 

 

 

 

Industrial T = –40oC to +85oC

3.0

3.6

V

 

 

 

A

 

 

 

VCCIO

Supply voltage for output drivers for 3.3V operation

3.0

3.6

V

 

 

Supply voltage for output drivers for 2.5V operation

2.3

2.7

V

 

 

 

 

 

 

 

 

VIL

Low-level input voltage

 

0

0.80

V

 

VIH

High-level input voltage

 

2.0

5.5

V

 

VO

Output voltage

 

0

VCCIO

V

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

TDR

Data Retention

20

-

Years

NPE

Program/Erase Cycles (Endurance)

10,000

-

Cycles

VESD

Electrostatic Discharge (ESD)

2,000

-

Volts

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

 

Test Conditions

Min

Max

Units

 

VOH

Output high voltage for 3.3V outputs

 

IOH = –4.0 mA

2.4

 

V

 

 

 

Output high voltage for 2.5V outputs

 

IOH = –500 A

90% VCCIO

 

V

 

VOL

Output low voltage for 3.3V outputs

 

IOL = 8.0 mA

-

0.4

V

 

 

 

Output low voltage for 2.5V outputs

 

IOL = 500 A

-

0.4

V

 

IIL

Input leakage current

 

VCC = Max

-

±10

A

 

 

 

 

 

VIN = GND or VCC

 

 

 

 

IIH

I/O high-Z leakage current

 

VCC = Max

-

±10

A

 

 

 

 

 

VIN = GND or VCC

 

 

 

 

CIN

I/O capacitance

 

VIN = GND

-

10

pF

 

 

 

 

 

f = 1.0 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC

Operating supply current

 

VI = GND, No load

20 (Typical)

mA

 

 

 

(low power mode, active)

 

f = 1.0 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS057 (v1.1) August 28, 2000

www.xilinx.com

 

 

3

 

Preliminary Product Specification

1-800-255-7778

 

 

 

 

Loading...
+ 5 hidden pages