9
December 4, 1998 (Version 5.0)
Features
•5 ns pin-to-pin logic delays on all pins
•fCNT to 100 MHz
•36 macrocells with 800 usable gates
•Up to 34 user I/O pins
•5 V in-system programmable (ISP)
-Endurance of 10,000 program/erase cycles
-Program/erase over full commercial voltage and temperature range
•Enhanced pin-locking architecture
•Flexible 36V18 Function Block
-90 product terms drive any or all of 18 macrocells within Function Block
-Global and product term clocks, output enables, set and reset signals
•Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
•Programmable power reduction mode in each macrocell
•Slew rate control on individual outputs
•User programmable ground pin capability
•Extended pattern security features for design protection
•High-drive 24 mA outputs
•3.3 V or 5 V I/O capability
•Advanced CMOS 5V FastFLASH technology
•Supports parallel programming of more than one XC9500 concurrently
•Available in 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Description
The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview.
XC9536 In-System Programmable
CPLD
Product Specification
Power Management
Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.
Operating current for each design can be approximated for specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
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(83) |
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High |
Performance |
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(mA) |
(50) |
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(50) |
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CC |
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I |
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Power |
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Typical |
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Low |
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(30) |
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0 50 100
Clock Frequency (MHz)
X5920
Figure 1: Typical ICC vs. Frequency For XC9536
December 4, 1998 (Version 5.0) |
1 |
XC9536 In-System Programmable CPLD
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3 |
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JTAG Port |
1 |
JTAG |
In-System Programming Controller |
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Controller |
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36 |
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18 |
Function |
I/O |
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Block 1 |
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I/O |
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Macrocells |
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1 to 18 |
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I/O |
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I/O |
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Matrix |
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36 |
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Function |
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18 |
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Switch |
Block 2 |
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Macrocells |
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I/O |
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1 to 18 |
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Blocks |
FastCONNECT |
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I/O |
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I/O |
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I/O |
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I/O |
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I/O/GCK |
3 |
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I/O/GSR |
1 |
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I/O/GTS |
2 |
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X5919
Figure 2: XC9536 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
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December 4, 1998 (Version 5.0) |
XC9536 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol |
Parameter |
Value |
Units |
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VCC |
Supply voltage relative to GND |
-0.5 to 7.0 |
V |
VIN |
DC input voltage relative to GND |
-0.5 to VCC + 0.5 |
V |
VTS |
Voltage applied to 3-state output with respect to GND |
-0.5 to VCC + 0.5 |
V |
TSTG |
Storage temperature |
-65 to +150 |
°C |
TSOL |
Max soldering temperature (10 s @ 1/16 in = 1.5 mm) |
+260 |
°C |
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions1
Symbol |
Parameter |
Min |
Max |
Units |
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VCCINT |
Supply voltage for internal logic and input buffer |
4.75 |
5.25 |
V |
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(4.5) |
(5.5) |
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VCCIO |
Supply voltage for output drivers for 5 V operation |
4.75 (4.5) |
5.25 (5.5) |
V |
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Supply voltage for output drivers for 3.3 V operation |
3.0 |
3.6 |
V |
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VIL |
Low-level input voltage |
0 |
0.80 |
V |
VIH |
High-level input voltage |
2.0 |
VCCINT +0.5 |
V |
VO |
Output voltage |
0 |
VCCIO |
V |
Note 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol |
Parameter |
Min |
Max |
Units |
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tDR |
Data Retention |
20 |
- |
Years |
NPE |
Program/Erase Cycles |
10,000 |
- |
Cycles |
December 4, 1998 (Version 5.0) |
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