XILINX XC95288XV-7FG256C, XC95288XV-7CS280C, XC95288XV-5TQ144C, XC95288XV-5PQ208C, XC95288XV-5FG256C Datasheet

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XC95288XV High-Performance

CPLD

DS050 (v2.2) August 27, 2001	Advance Product Specification

Features

•288 macrocells with 6,400 usable gates

•Available in small footprint packages

-144-pin TQFP (117 user I/O pins)

-208-pin PQFP (168 user I/O pins)

-280-pin CSP (192 user I/O pins)

-256-pin FBGA (192 user I/O pins)

•Optimized for high-performance 2.5V systems

-Low power operation

-Multi-voltage operation

•Advanced system features

-In-system programmable

-Four separate output banks

-Superior pin-locking and routability with FastCONNECT II™ switch matrix

-Extra wide 54-input Function Blocks

-Up to 90 product-terms per macrocell with individual product-term allocation

-Local clock inversion with three global and one product-term clocks

-Individual output enable per output pin

-Input hysteresis on all user and boundary-scan pin inputs

-Bus-hold ciruitry on all user pin inputs

-Full IEEE Standard 1149.1 boundary-scan (JTAG)

•Fast concurrent programming

•Slew rate control on individual outputs

•Enhanced data security features

•Excellent quality and reliability

-Endurance exceeding 10,000 program/erase cycles

-20 year data retention

-ESD protection exceeding 2,000V

Description

The XC95288XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 5 ns.

Power Estimation

Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.

For a general estimate of ICC, the following equation may be used:

ICC (mA) =

MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f

Where:

MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation.

Figure 1 shows the above estimation in a graphical form.

	450
	400
	350					200 MHz
(mA)	300
CC	250
			ance
I
Typical
	200	rform
		e
		P		120 MHz
	igh
	H
	150		r
			e
		Low	Pow
	100
	50
	0
	50		100	150	200	250

Clock Frequency (MHz)

DS050_01_012501

Figure 1: Typical ICC vs. Frequency for XC95288XV

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Advance Product Specification	1-800-255-7778

XC95288XV High-Performance CPLD

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			3
	JTAG Port	1	JTAG	In-System Programming Controller
			Controller

				54
			18	Function
	I/O			Block 1
	I/O			Macrocells
				1 to 18
	I/O
	I/O	Matrix		54
				Function
			18
				Block 2
		II Switch		Macrocells
	I/O			1 to 18
	Blocks
	I/O	FastCONNECT		54
	I/O		18	Function
				Block 3
	I/O			Macrocells
	I/O			1 to 18
	3
	I/O/GCK			54
	1		18	Function
	I/O/GSR			Block 4
	4			Macrocells
	I/O/GTS			1 to 18
				54
			18	Function
				Block 16
				Macrocells
				1 to 18
				DS055_02_101300

Figure 2: XC95288XV Architecture

(Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.)

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XC95288XV High-Performance CPLD

Absolute Maximum Ratings

Symbol	Description	Value	Units
VCC	Supply voltage relative to GND	–0.5 to 2.7	V
VCCIO	Supply voltage for output drivers	–0.5 to 3.6	V
VIN	Input voltage relative to GND(1)	–0.5 to 3.6	V
VTS	Voltage applied to 3-state output(1)	–0.5 to 3.6	V
T	Storage temperature (ambient)	–65 to +150	oC
STG
T	Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)	+260	oC
SOL
T	Junction temperature	+150	oC
J

Notes:

1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +3.6V, provided this overor undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

2.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol		Parameter		Min	Max	Units
V	CCINT	Supply voltage for internal logic	Commercial T = 0oC to +70oC	2.37	2.62	V
		and input buffers	A
			Industrial T = –40oC to +85oC	2.37	2.62
			A
VCCIO		Supply voltage for output drivers for 3.3V operation		3.13	3.46	V
		Supply voltage for output drivers for 2.5V operation		2.37	2.62	V
		Supply voltage for output drivers for 1.8V operation		1.71	1.89	V
	VIL	Low-level input voltage		0	0.8	V
	VIH	High-level input voltage		1.7	3.6	V
	VO	Output voltage		0	VCCIO	V

Quality and Reliability Characteristics

Symbol	Parameter	Min	Max	Units
TDR	Data retention	20	-	Years
NPE	Program/Erase cycles (endurance)	10,000	-	Cycles
VESD	Electrostatic Discharge (ESD)	2,000	-	Volts

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DC Characteristics Over Recommended Operating Conditions

Symbol		Parameter	Test Conditions	Min	Max	Units
VOH		Output high voltage for 3.3V outputs	IOH = –4.0 mA	2.4	-	V
		Output high voltage for 2.5V outputs	IOH = –1.0 mA	2.0	-	V
		Output high voltage for 1.8V outputs	IOH = –100 A	90%	-	V
				VCCIO
VOL		Output low voltage for 3.3V outputs	IOL = 8.0 mA	-	0.4	V
		Output low voltage for 2.5V outputs	IOL = 1.0 mA	-	0.4	V
		Output low voltage for 1.8V outputs	IOL = 100 A	-	0.4	V
IIL		Input leakagelow current	VCC = 2.62V	-	10	A
			VCCIO = 3.6V
			VIN = GND or 3.6V
IIH		Input leakage high current	VCC = 2.62V	-	10	A
			VCCIO = 3.6V
			VIN = GND or 3.6V
CIN		I/O capacitance	VIN = GND	-	10	pF
			f = 1.0 MHz
ICC		Operating Supply Current	VI = GND, No load	59		mA
		(low power mode, active)	f = 1.0 MHz

AC Characteristics

		XC95288XV-5		XC95288XV-7			XC95288XV-10
Symbol	Parameter								Units
		Min	Max	Min		Max	Min	Max
TPD	I/O to output valid	-	5.0	-		7.5	-	10	ns
TSU	I/O setup time before GCK	3.5	-	4.8		-	6.5	-	ns
TH	I/O hold time after GCK	0	-	0		-	0	-	ns
TCO	GCK to output valid	-	3.5	-		4.5	-	5.8	ns
fSYSTEM	Multiple FB internal operating	-	222.2	-		125.0	-	100.0	MHz
	frequency
TPSU	I/O setup time before p-term clock	1.0	-	1.6		-	2.1	-	ns
	input
TPH	I/O hold time after p-term clock input	2.5	-	3.2		-	4.4	-	ns
TPCO	P-term clock output valid	-	6.0	-		7.7	-	10.2	ns
TOE	GTS to output valid	-	4.0	-		5.0	-	7.0	ns
TOD	GTS to output disable	-	4.0	-		5.0	-	7.0	ns
TPOE	Product term OE to output enabled	-	7.0	-		9.5	-	11.0	ns
TPOD	Product term OE to output disabled	-	7.0	-		9.5	-	11.0	ns
TAO	GSR to output valid	-	10.0	-		12.0	-	14.5	ns
TPAO	P-term S/R to output valid	-	10.7	-		12.6	-	15.3	ns
TWLH	GCK pulse width (High or Low)	2.2	-	4.0		-	5.0	-	ns
TPLH	P-term clock pulse width (High or Low)	5.0	-	6.5		-	7.0	-	ns
		Advance Information			Preliminary Information

Notes:

1.Please contact Xilinx for up-to-date information on advance specifications.

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