XILINX XC95144-15PQ100I, XC95144-15PQ100C, XC95144-10TQ100I, XC95144-10TQ100C, XC95144-10PQ160I Datasheet

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December 4, 1998 (Version 4.0)

Features

7.5 ns pin-to-pin logic delays on all pins

fCNT to 111 MHz

144 macrocells with 3,200 usable gates

Up to 133 user I/O pins

5 V in-system programmable

-Endurance of 10,000 program/erase cycles

-Program/erase over full commercial voltage and temperature range

Enhanced pin-locking architecture

Flexible 36V18 Function Block

-90 product terms drive any or all of 18 macrocells within Function Block

-Global and product term clocks, output enables, set and reset signals

Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

Programmable power reduction mode in each macrocell

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design protection

High-drive 24 mA outputs

3.3 V or 5 V I/O capability

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one XC9500 concurrently

Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages

Description

The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

Power Management

Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

XC95144 In-System Programmable

CPLD

Product Specification

Operating current for each design can be approximated for specific operating conditions using the following equation:

ICC (mA) =

MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f

Where:

MCHP = Macrocells in high-performance mode

MCLP = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

Figure 1 shows a typical calculation for the XC95144 device.

 

600

 

 

 

 

(480)

 

 

 

 

 

 

 

 

 

 

 

 

400

 

Performance

 

 

(mA)

High

 

 

 

 

 

 

 

 

 

(320)

CC

 

 

 

 

 

(300)

 

 

 

 

 

I

 

 

 

 

 

Typical

200

Low

Power

 

 

 

 

 

 

 

 

(160)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

50

100

 

 

Clock Frequency (MHz)

X5898B

 

 

 

 

 

Figure 1: Typical Icc vs. Frequency for XC95144

December 4, 1998 (Version 4.0)

1

XILINX XC95144-15PQ100I, XC95144-15PQ100C, XC95144-10TQ100I, XC95144-10TQ100C, XC95144-10PQ160I Datasheet

XC95144 In-System Programmable CPLD

 

 

3

 

JTAG Port

1

JTAG

In-System Programming Controller

Controller

 

 

 

 

 

 

 

 

36

 

 

 

 

18

Function

I/O

 

 

 

Block 1

I/O

 

 

 

 

Macrocells

 

 

 

 

1 to 18

 

 

 

 

 

I/O

 

 

 

 

 

I/O

 

 

Matrix

 

36

 

 

 

Function

 

 

 

18

 

 

 

Block 2

 

 

 

 

 

 

 

 

Switch

 

Macrocells

 

 

I/O

 

1 to 18

 

 

Blocks

 

 

 

 

FastCONNECT

 

 

I/O

 

 

 

36

 

 

 

 

I/O

 

 

18

Function

 

 

Block 3

 

 

 

I/O

 

 

 

Macrocells

 

 

 

 

1 to 18

 

 

 

 

 

I/O

 

 

 

 

 

I/O/GCK

3

 

 

 

 

 

 

 

 

36

 

1

 

 

18

Function

I/O/GSR

 

 

Block 4

 

 

 

I/O/GTS

2

 

 

 

Macrocells

 

 

 

 

1 to 18

 

 

 

 

 

36

 

 

 

 

18

Function

 

 

 

 

Block 8

 

 

 

 

 

Macrocells

 

 

 

 

 

1 to 18

 

 

 

 

 

X5922

Figure 2: XC95144 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

2

December 4, 1998 (Version 4.0)

XC95144 In-System Programmable CPLD

Absolute Maximum Ratings

Symbol

Parameter

Value

Units

 

 

 

 

VCC

Supply voltage relative to GND

-0.5 to 7.0

V

VIN

DC input voltage relative to GND

-0.5 to VCC + 0.5

V

VTS

Voltage applied to 3-state output with respect to GND

-0.5 to VCC + 0.5

V

TSTG

Storage temperature

-65 to +150

°C

TSOL

Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

+260

°C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions1

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

VCCINT

Supply voltage for internal logic and input buffer

4.75

5.25

V

 

 

(4.5)

(5.5)

 

VCCIO

Supply voltage for output drivers for 5 V operation

4.75 (4.5)

5.25 (5.5)

V

 

Supply voltage for output drivers for 3.3 V operation

3.0

3.6

V

 

 

 

 

 

VIL

Low-level input voltage

0

0.80

V

VIH

High-level input voltage

2.0

VCCINT +0.5

V

VO

Output voltage

0

VCCIO

V

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

tDR

Data Retention

20

-

Years

NPE

Program/Erase Cycles

10,000

-

Cycles

December 4, 1998 (Version 4.0)

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