XILINX XC5215-5PG299C, XC5215-5HQ240C, XC5215-5HQ208C, XC5215-5BG352C, XC5215-5BG225C Datasheet

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XC5200 Series

Field Programmable Gate Arrays

November 5, 1998 (Version 5.2)

Product Specification

 

 

Features

Low-cost, register/latch rich, SRAM based reprogrammable architecture

-0.5 m three-layer metal CMOS process technology

-256 to 1936 logic cells (3,000 to 23,000 “gates”)

-Price competitive with Gate Arrays

System Level Features

-System performance beyond 50 MHz

-6 levels of interconnect hierarchy

-VersaRingI/O Interface for pin-locking

-Dedicated carry logic for high-speed arithmetic functions

-Cascade chain for wide input functions

-Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins

-Internal 3-state bussing capability

-Four dedicated low-skew clock or signal distribution nets

Versatile I/O and Packaging

-Innovative VersaRingI/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals

-Programmable output slew-rate control maximizes performance and reduces noise

-Zero Flip-Flop hold time for input registers simplifies system timing

-Independent Output Enables for external bussing

-Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series

-Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available

Fully Supported by Xilinx Development System

-Automatic place and route software

-Wide selection of PC and Workstation platforms

-Over 100 3rd-party Alliance interfaces

-Supported by shrink-wrap Foundation software

Description

 

The XC5200 Field-Programmable Gate Array Family is

 

engineered to deliver low cost. Building on experiences

 

gained with three previous successful SRAM FPGA fami-

 

lies, the XC5200 family brings a robust feature set to pro-

 

grammable logic design. The VersaBlocklogic module,

 

the VersaRing I/O interface, and a rich hierarchy of inter-

 

connect resources combine to enhance design flexibility

 

and reduce time-to-market. Complete support for the

7

XC5200 family is delivered through the familiar Xilinx soft-

 

ware environment. The XC5200 family is fully supported on

 

popular workstation and PC platforms. Popular design

 

entry methods are fully supported, including ABEL, sche-

 

matic capture, VHDL, and Verilog HDL synthesis. Design-

 

ers utilizing logic synthesis can use their existing tools to

 

design with the XC5200 devices.

 

.

Table 1: XC5200 Field-Programmable Gate Array Family Members

Device

XC5202

XC5204

XC5206

XC5210

XC5215

 

 

 

 

 

 

Logic Cells

256

480

784

1,296

1,936

 

 

 

 

 

 

Max Logic Gates

3,000

6,000

10,000

16,000

23,000

 

 

 

 

 

 

Typical Gate Range

2,000 - 3,000

4,000 - 6,000

6,000 - 10,000

10,000 - 16,000

15,000 - 23,000

 

 

 

 

 

 

VersaBlock Array

8 x 8

10 x 12

14 x 14

18 x 18

22 x 22

 

 

 

 

 

 

CLBs

64

120

196

324

484

 

 

 

 

 

 

Flip-Flops

256

480

784

1,296

1,936

 

 

 

 

 

 

I/Os

84

124

148

196

244

 

 

 

 

 

 

TBUFs per Longline

10

14

16

20

24

 

 

 

 

 

 

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XC5200 Series Field Programmable Gate Arrays

XC5200 Family Compared to XC4000/Spartan™ and XC3000 Series

For readers already familiar with the XC4000/Spartan and XC3000 FPGA Families, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, comparisons refer to both XC4000/Spartan and XC3000 devices.

Configurable Logic Block (CLB) Resources

Each XC5200 CLB contains four independent 4-input function generators and four registers, which are configured as four independent Logic Cells™ (LCs). The registers in each XC5200 LC are optionally configurable as edge-triggered D-type flip-flops or as transparent level-sensitive latches.

The XC5200 CLB includes dedicated carry logic that provides fast arithmetic carry capability. The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions.

XC4000 family: XC5200 devices have no wide edge decoders. Wide decoders are implemented using cascade logic. Although sacrificing speed for some designs, lack of wide edge decoders reduces the die area and hence cost of the XC5200.

XC4000/Spartan family: XC5200 dedicated carry logic differs from that of the XC4000/Spartan family in that the sum is generated in an additional function generator in the adjacent column. This design reduces XC5200 die size and hence cost for many applications. Note, however, that a loadable up/down counter requires the same number of function generators in both families. XC3000 has no dedicated carry.

XC4000/Spartan family: XC5200 lookup tables are optimized for cost and hence cannot implement RAM.

Table 2: Xilinx Field-Programmable Gate Array

Families

Parameter

XC5200

Spartan

XC4000

XC3000

 

 

 

 

 

CLB function

4

3

3

2

generators

 

 

 

 

 

 

 

 

 

CLB inputs

20

9

9

5

 

 

 

 

 

CLB outputs

12

4

4

2

 

 

 

 

 

Global buffers

4

8

8

2

 

 

 

 

 

User RAM

no

yes

yes

no

 

 

 

 

 

Edge decoders

no

no

yes

no

 

 

 

 

 

Cascade chain

yes

no

no

no

 

 

 

 

 

Fast carry logic

yes

yes

yes

no

 

 

 

 

 

Internal 3-state

yes

yes

yes

yes

 

 

 

 

 

Boundary scan

yes

yes

yes

no

 

 

 

 

 

Slew-rate control

yes

yes

yes

yes

 

 

 

 

 

Routing Resources

The XC5200 family provides a flexible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the CLB, a Local Interconnect Matrix (LIM), and direct connects to neighboring VersaBlocks.

The XC5200 provides four global buffers for clocking or high-fanout control signals. Each buffer may be sourced by means of its dedicated pad or from any internal source.

Each XC5200 TBUF can drive up to two horizontal and two vertical Longlines. There are no internal pull-ups for XC5200 Longlines.

Input/Output Block (IOB) Resources

The XC5200 family maintains footprint compatibility with the XC4000 family, but not with the XC3000 family.

To minimize cost and maximize the number of I/O per Logic Cell, the XC5200 I/O does not include flip-flops or latches.

For high performance paths, the XC5200 family provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers.

Each XC5200 I/O Pin provides a programmable delay element to control input set-up time. This element can be used to avoid potential hold-time problems. Each XC5200 I/O Pin is capable of 8-mA source and sink currents.

IEEE 1149.1-type boundary scan is supported in each XC5200 I/O.

Configuration and Readback

The XC5200 supports a new configuration mode called Express mode.

XC4000/Spartan family: The XC5200 family provides a global reset but not a global set.

XC5200 devices use a different configuration process than that of the XC3000 family, but use the same process as the XC4000 and Spartan families.

XC3000 family: Although their configuration processes differ, XC5200 devices may be used in daisy chains with XC3000 devices.

XC3000 family: The XC5200 PROGRAM pin is a sin- gle-function input pin that overrides all other inputs. The PROGRAM pin does not exist in XC3000.

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XC5200 Series Field Programmable Gate Arrays

XC3000 family: XC5200 devices support an additional programming mode: Peripheral Synchronous.

XC3000 family: The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flip-flops.

XC3000 family: The XC5200 family does not provide an on-chip crystal oscillator amplifier, but it does provide an internal oscillator from which a variety of frequencies up to 12 MHz are available.

Architectural Overview

Figure 1 presents a simplified, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, programmable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks (Figure 2). General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM).

Input/Output Blocks (IOBs)

 

 

VersaRing

 

 

 

GRM

GRM

GRM

 

 

Versa-

Versa-

Versa-

 

 

Block

Block

Block

 

VersaRing

GRM

GRM

GRM

VersaRing

Versa-

Versa-

Versa-

Block

Block

Block

 

 

 

 

GRM

GRM

GRM

 

 

Versa-

Versa-

Versa-

 

 

Block

Block

Block

 

 

 

VersaRing

 

 

X4955

Figure 1: XC5200 Architectural Overview

VersaBlock: Abundant Local Routing Plus

 

 

 

 

 

 

 

Versatile Logic

 

 

GRM

 

 

 

 

The basic logic element in each VersaBlock structure is the

 

 

4

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Logic Cell, shown in Figure 3. Each LC contains a 4-input

 

 

24

 

 

 

7

 

 

 

 

 

 

function generator (F), a storage device (FD), and control

 

 

 

TS

 

 

 

logic. There are five independent inputs and three outputs

 

 

 

CLB

 

 

 

 

 

 

LC3

 

 

to each LC. The independence of the inputs and outputs

 

 

 

 

 

 

 

 

 

4

 

 

allows the software to maximize the resource utilization

 

 

4

LC2

4

 

 

 

4

LC1

4

 

within each LC. Each Logic Cell also contains a direct

 

 

 

 

 

 

 

 

LC0

 

 

feedthrough path that does not sacrifice the use of either

 

 

 

 

 

 

 

 

 

 

 

 

the function generator or the register; this feature is a first

 

 

 

 

LIM

 

 

for FPGAs. The storage device is configurable as either a D

 

 

 

4

4

 

 

flip-flop or a latch. The control logic consists of carry logic

 

 

 

 

 

 

 

 

 

 

 

 

for fast implementation of arithmetic functions, which can

 

 

 

Direct Connects

X5707

 

also be configured as a cascade chain allowing decode of

 

 

 

 

 

 

 

very wide input functions.

Figure 2:

VersaBlock

 

 

 

 

 

 

CO

 

 

 

 

 

DI

 

 

 

 

 

DO

 

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

F4

 

 

 

 

FD

 

 

 

 

 

 

 

 

 

F3

 

 

 

 

 

 

 

F2

F

 

 

 

 

 

 

F1

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

CI

 

CE CK

CLR

 

 

 

 

 

 

 

 

X4956

 

Figure 3: XC5200 Logic Cell (Four LCs per CLB)

 

November 5, 1998 (Version 5.2)

 

 

 

 

 

 

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XC5200 Series Field Programmable Gate Arrays

The XC5200 CLB consists of four LCs, as shown in Figure 4. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be configured to implement 5-input functions. The challenge of FPGA implementation software has always been to maximize the usage of logic resources. The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect — the Local Interconnect Matrix (LIM) and direct connects. These two interconnect resources, combined with the CLB, form the VersaBlock, represented in Figure 2.

LC3

CO

 

 

 

 

 

DI

 

 

 

DO

 

 

 

 

 

 

 

D

Q

F4

 

 

 

FD

 

 

 

 

F3

 

 

 

 

F2

F

 

 

 

F1

 

 

 

 

 

 

 

 

X

LC2

 

 

 

DI

 

 

 

DO

 

 

 

 

 

 

 

D

Q

F4

 

 

 

FD

 

 

 

 

F3

 

 

 

 

F2

F

 

 

 

F1

 

 

 

 

 

 

 

 

X

LC1

 

 

 

DI

 

 

 

DO

 

 

 

 

 

 

 

D

Q

F4

 

 

 

FD

 

 

 

 

F3

 

 

 

 

F2

F

 

 

 

F1

 

 

 

 

 

 

 

 

X

LC0

 

 

DO

DI

 

 

 

 

 

 

 

 

 

 

D

Q

F4

 

 

 

FD

 

 

 

 

F3

 

 

 

 

F2

F

 

 

 

F1

 

 

 

 

 

 

 

 

X

 

 

CI

CE CK CLR

 

X4957

Figure 4: Configurable Logic Block

The LIM provides 100% connectivity of the inputs and outputs of each LC in a given CLB. The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes.

The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general interconnect. These two layers of local routing resource improve the granularity of the architecture, effectively making the XC5200 family a “sea of logic cells.” Each Versa-Block has four 3-state buffers that share a common enable line and directly drive horizontal and vertical Longlines, creating robust on-chip bussing capability. The VersaBlock allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion. These resources also minimize local routing congestion and improve the efficiency of the general interconnect, which is used for connecting larger groups of logic. It is this combination of both fine-grain and coarse-grain architecture attributes that maximize logic utilization in the XC5200 family. This symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions.

VersaRing I/O Interface

The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the I/O-to-gate ratio and decreasing the cost per I/O. A “freeway” of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic. These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement flexibility. These incremental edge resources give users increased flexibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manufactured concurrent with the logic design.

General Routing Matrix

The GRM is functionally similar to the switch matrices found in other architectures, but it is novel in its tight coupling to the logic resources contained in the VersaBlocks. Advanced simulation tools were used during the development of the XC5200 architecture to determine the optimal level of routing resources required. The XC5200 family contains six levels of interconnect hierarchy — a series of

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XC5200 Series Field Programmable Gate Arrays

single-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained within each Versa-Block. Throughout the XC5200 interconnect, an efficient multiplexing scheme, in combination with three layer metal (TLM), was used to improve the overall efficiency of silicon usage.

Performance Overview

The XC5200 family has been benchmarked with many designs running synchronous clock rates beyond 66 MHz. The performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the interconnect routing. A rough estimate of timing can be made by assuming 3-6 ns per logic level, which includes direct-con- nect routing delays, depending on speed grade. More accurate estimations can be made using the information in the Switching Characteristic Guideline section.

Taking Advantage of Reconfiguration

FPGA devices can be reconfigured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic.

Hardware can be changed as easily as software. Design updates or modifications are easy, and can be made to products already in the field. An FPGA can even be reconfigured dynamically to perform different functions at different times.

Reconfigurable logic can be used to implement system self-diagnostics, create systems capable of being reconfigured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benefit, using reconfigurable FPGA devices simplifies hardware design and debugging and shortens product time-to-market.

Detailed Functional Description

Configurable Logic Blocks (CLBs)

Figure 4 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a D-Type flip-flop or latch with common clock, clock enable, and clear, but individually selectable clock polarity. Additional logic features provided in the CLB are:

An independent 5-input LUT by combining two 4-input LUTs.

High-speed carry propagate logic.

High-speed pattern decoding.

High-speed direct connection to flip-flop D-inputs.

Individual selection of either a transparent, level-sensitive latch or a D flip-flop.

Four 3-state buffers with a shared Output Enable.

5-Input Functions

Figure 5 illustrates how the outputs from the LUTs from LC0 and LC1 can be combined with a 2:1 multiplexer (F5_MUX) to provide a 5-input function. The outputs from the LUTs of LC2 and LC3 can be similarly combined.

7

 

 

CO

 

 

 

 

 

 

DI

 

 

 

 

DO

 

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

 

 

FD

 

I1

F4

 

 

 

 

 

 

F3

 

 

 

 

 

 

I2

 

 

 

 

 

 

F2

F

 

 

 

 

 

I3

 

 

 

X

 

F1

 

 

 

 

 

I4

 

 

 

 

 

 

 

 

 

 

 

LC1

 

 

 

F5_MUX

 

 

 

 

 

 

DI

 

 

 

 

DO

out

I5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

Qout

 

 

 

 

 

 

 

 

 

 

 

 

 

FD

 

 

F4

 

 

 

 

 

 

 

F3

 

 

 

 

 

 

 

F2

F

 

 

 

X

 

 

F1

 

 

 

 

 

 

 

 

 

 

LC0

 

 

 

CI

CE

CK

CLR

 

5-Input Function

X5710

Figure 5: Two LUTs in Parallel Combined to Create a 5-input Function

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

carry out

A3

 

 

CO

 

DO

carry3

 

 

CO

 

DO

DI

 

 

 

DI

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

D

Q

B3

 

 

 

 

 

 

 

 

F4

 

CY_MUX

 

FD

 

F4

 

 

 

FD

 

 

 

 

 

 

 

 

 

A3 and B3

F3

XOR

 

 

 

 

F3

 

 

 

 

F2

 

 

 

 

F2

XOR

 

 

 

to any two

 

 

 

 

 

 

 

 

 

 

 

half sum3

 

 

 

 

F1

 

 

 

X

F1

 

 

 

X

 

 

 

 

 

LC3

carry2

 

 

 

 

LC3

A2

DI

 

 

 

DO

DI

 

 

 

DO

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B2

 

 

 

D

Q

 

 

 

 

D

Q

 

F4

 

CY_MUX

 

FD

 

F4

 

 

 

FD

 

 

 

 

 

 

 

 

 

 

A2 and B2

F3

XOR

 

 

 

 

F3

 

 

 

 

F2

 

 

 

 

F2

XOR

 

 

 

to any two

 

 

X

half sum2

 

 

 

 

F1

 

 

 

F1

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

LC2

carry1

 

 

 

 

LC2

A1

DI

 

 

 

DO

DI

 

 

 

DO

or

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

D

Q

B1

 

 

 

 

 

 

 

 

F4

 

CY_MUX

 

FD

 

F4

 

 

 

FD

 

 

 

 

 

 

 

 

 

A1 and B1

F3

 

 

 

 

 

F3

 

 

 

 

F2

XOR

 

 

 

 

F2

XOR

 

 

 

to any two

 

 

 

half sum1

 

 

 

 

F1

 

 

 

X

F1

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

LC1

carry0

 

 

 

 

LC1

A0

DI

 

 

 

DO

DI

 

 

 

DO

or

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

 

B0

 

 

 

 

 

 

 

D

Q

 

F4

 

CY_MUX

 

FD

 

F4

 

 

 

FD

 

 

 

 

 

 

 

 

 

 

 

F3

 

 

 

 

 

 

 

 

 

A0 and B0

 

 

 

 

 

F3

 

 

 

 

F2

XOR

 

 

 

 

 

 

 

 

to any two

 

 

X

half sum0

F2

XOR

 

 

 

 

F1

 

 

 

F1

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CI

CE CK

CLR

LC0

 

 

CI

CE CK

CLR

LC0

0

 

 

carry in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F=0

 

CY_MUX

 

 

 

 

 

 

 

 

 

 

Initialization of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

carry chain (One Logic Cell)

 

 

 

 

 

 

 

sum3

sum2

sum1

sum0

X5709

Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate

Carry Function

The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) symbol is used to indicate the XC5200 carry logic. This symbol represents the dedicated 2:1 multiplexer in each LC that performs the one-bit high-speed carry propagate per logic cell (four bits per CLB).

While the carry propagate is performed inside the LC, an adjacent LC must be used to complete the arithmetic function. Figure 6 represents an example of an adder function. The carry propagate is performed on the CLB shown,

which also generates the half-sum for the four-bit adder. An adjacent CLB is responsible for XORing the half-sum with the corresponding carry-out. Thus an adder or counter requires two LCs per bit. Notice that the carry chain requires an initialization stage, which the XC5200 family accomplishes using the carry initialize (CY_INIT) macro and one additional LC. The carry chain can propagate vertically up a column of CLBs.

The XC5200 library contains a set of Relationally-Placed Macros (RPMs) and arithmetic functions designed to take advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement cus-

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XC5200 Series Field Programmable Gate Arrays

tomized RPMs, freeing the designer from the need to become an expert on architectures.

results or other incoming data in flip-flops, and connect their outputs to the interconnect network as well. The CLB storage elements can also be configured as latches.

cascade out

Table 3: CLB Storage Element Functionality

 

 

 

 

 

 

 

 

(active rising edge is shown)

 

 

 

 

 

 

CO

 

 

 

Mode

CK

CE

CLR

D

Q

 

DI

 

 

 

 

DO

 

 

 

 

 

out

 

 

 

 

 

 

 

 

 

 

 

D

Q

Power-Up or

X

X

X

X

0

 

 

 

CY_MUX

 

 

FD

GR

A15

F4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

X

1

X

0

A14

F3

 

 

 

 

 

 

A13

F2

AND

 

 

 

 

Flip-Flop

__/

1*

0*

D

D

A12

F1

 

 

 

 

X

 

 

 

 

 

 

LC3

 

0

X

0*

X

Q

 

DI

 

 

 

 

DO

 

1

1*

0*

X

Q

 

 

 

 

D

Q

Latch

 

 

 

 

 

0

1*

0*

D

D

 

 

 

CY_MUX

 

 

FD

 

A11

F4

 

 

 

Both

X

0

0*

X

Q

 

 

 

 

 

A10

F3

 

 

 

 

 

Legend:

 

 

 

 

 

A9

F2

AND

 

 

 

 

 

 

 

 

 

A8

F1

 

 

 

 

X

X

Don’t care

 

 

 

 

 

 

 

 

 

 

LC2

__/

Rising edge

 

 

 

 

 

DI

 

 

 

 

 

0*

Input is Low or unconnected (default value)

 

 

 

 

 

 

DO

1*

Input is High or unconnected (default value)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

 

A7

F4

 

CY_MUX

 

 

FD

Data Inputs and Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

F3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

F2

AND

 

 

 

 

The source of a storage element data input is programma-

A4

F1

 

 

 

 

X

 

 

 

 

ble. It is driven by the function F, or by the Direct In (DI)

 

 

 

 

 

 

LC1

 

 

 

 

 

 

block input. The flip-flops or latches drive the Q CLB out-

 

 

 

 

 

 

DO

 

DI

 

 

 

 

puts.

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

F4

 

CY_MUX

 

 

FD

Four fast feed-through paths from DI to DO are available,

 

 

 

 

 

 

 

 

 

as shown in Figure 4. This bypass is sometimes used by

A2

F3

AND

 

 

 

 

A1

F2

 

 

 

 

the automated router to repower internal signals. In addi-

A0

F1

 

 

 

 

X

 

 

 

 

tion to the storage element (Q) and direct (DO) outputs,

 

 

CI

CE

CK

CLR

LC0

 

 

there is a combinatorial output (X) that is always sourced

 

 

 

cascade in

 

 

 

 

 

 

 

 

 

 

by the Lookup Table.

 

 

 

 

 

 

 

CY_MUX

 

 

 

The four edge-triggered D-type flip-flops or level-sensitive

 

F=0

 

Initialization of

 

 

 

 

 

 

carry chain (One Logic Cell)

 

X5708

latches have common clock (CK) and clock enable (CE)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

inputs. Any of the clock inputs can also be permanently

Figure 7: XC5200 CY_MUX Used for Decoder Cascade

enabled. Storage element functionality

is described in

Table 3.

 

 

 

 

 

Logic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cascade Function

Each CY_MUX can be connected to the CY_MUX in the adjacent LC to provide cascadable decode logic. Figure 7 illustrates how the 4-input function generators can be configured to take advantage of these four cascaded CY_MUXes. Note that AND and OR cascading are specific cases of a general decode. In AND cascading all bits are decoded equal to logic one, while in OR cascading all bits are decoded equal to logic zero. The flexibility of the LUT achieves this result. The XC5200 library contains gate macros designed to take advantage of this function.

CLB Flip-Flops and Latches

The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial

Clock Input

The flip-flops can be triggered on either the rising or falling clock edge. The clock pin is shared by all four storage elements with individual polarity control. Any inverter placed on the clock input is automatically absorbed into the CLB.

Clock Enable

The clock enable signal (CE) is active High. The CE pin is shared by the four storage elements. If left unconnected for any, the clock enable for that storage element defaults to the active state. CE is not invertible within the CLB.

Clear

An asynchronous storage element input (CLR) can be used to reset all four flip-flops or latches in the CLB. This input

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XC5200 Series Field Programmable Gate Arrays

can also be independently disabled for any flip-flop. CLR is active High. It is not invertible within the CLB.

 

 

 

STARTUP

 

PAD

 

 

GR

Q2

 

 

 

 

 

 

 

GTS

Q3

 

 

IBUF

 

 

 

Q1Q4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK DONEIN

 

 

 

 

 

 

 

 

 

 

 

X9009

Figure 8: Schematic Symbols for Global Reset

Global Reset

A separate Global Reset line clears each storage element during power-up, reconfiguration, or when a dedicated Reset net is driven active. This global net (GR) does not compete with other routing resources; it uses a dedicated distribution network.

GR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GR pin of the STARTUP symbol. (See Figure 9.) A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-program- mable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Reset signal. Alternatively, GR can be driven from any internal node.

Using FPGA Flip-Flops and Latches

The abundance of flip-flops in the XC5200 Series invites pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results through pipeline flip-flops. This method should be seriously considered wherever throughput is more important than latency.

To include a CLB flip-flop, place the appropriate library symbol. For example, FDCE is a D-type flip-flop with clock enable and asynchronous clear. The corresponding latch symbol is called LDCE.

In XC5200-Series devices, the flip-flops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task. This ability increases the functional capacity of the devices.

The CLB setup time is specified between the function generator inputs and the clock input CK. Therefore, the specified CLB flip-flop setup time includes the delay through the function generator.

Three-State Buffers

The XC5200 family has four dedicated Three-State Buffers (TBUFs, or BUFTs in the schematic library) per CLB (see Figure 9). The four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. When in 3-state mode the CLB output enable (TS) control signal drives the enable to all four buffers. Each TBUF can drive up to two horizontal and/or two vertical Longlines. These 3-state buffers can be used to implement multiplexed or bidirectional buses on the horizontal or vertical longlines, saving logic resources.

The 3-state buffer enable is an active-High 3-state (i.e. an active-Low enable), as shown in Table 4.

Table 4: Three-State Buffer Functionality

IN

T

OUT

 

 

 

X

1

Z

 

 

 

IN

0

IN

 

 

 

Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array.

The longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undefined floating levels. However, it is overridden by any driver. To ensure the longline goes high when no buffers are on, add an additional BUFT to drive the output High during all of the previously undefined states.

Figure 10 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal.

TS

CLB

CLB

LC3

LC2

LC1

LC0

Horizontal

Longlines

X9030

Figure 9: XC5200 3-State Buffers

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XC5200 Series Field Programmable Gate Arrays

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~100 kΩ

Z = DA • A + DB • B + DC • C + DN • N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DA

 

 

 

 

DB

 

 

 

 

 

 

 

 

 

DC

 

 

 

 

DN

 

 

 

 

 

 

 

BUFT

 

 

BUFT

 

BUFT

 

BUFT

 

A

 

 

 

B

 

 

 

 

 

 

 

C

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X6466

"Weak Keeper"

Figure 10: 3-State Buffers Implement a Multiplexer

Input/Output Blocks

User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be configured for input, output, or bidirectional signals.

The I/O block, shown in Figure 11, consists of an input buffer and an output buffer. The output driver is an 8-mA full-rail CMOS buffer with 3-state control. Two slew-rate control modes are supported to minimize bus transients. Both the output buffer and the 3-state control are invertible. The input buffer has globally selected CMOS or TTL input thresholds. The input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip set-up and hold times. Minimum ESD protection is 3 KV using the Human Body Model.

 

Vcc

Delay

 

Input

 

Buffer

 

Pullup

 

I

 

 

PAD

Output

 

 

Buffer

 

Pulldown

 

O

 

 

T

X9001

Slew Rate

 

Control

 

 

 

Figure 11: XC5200 I/O Block

IOB Input Signals

The XC5200 inputs can be globally configured for either TTL (1.2V) or CMOS thresholds, using an option in the bitstream generation software. There is a slight hysteresis of about 300mV.

The inputs of XC5200-Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode.

Supported sources for XC5200-Series device inputs are shown in Table 5.

Table 5: Supported Sources for XC5200-Series Device Inputs

 

XC5200 Input Mode

Source

5 V,

5 V,

TTL

CMOS

 

Any device, Vcc = 3.3 V,

 

 

CMOS outputs

Unreliable

 

Any device, Vcc = 5 V,

Data

TTL outputs

 

 

 

Any device, Vcc = 5 V,

CMOS outputs

 

 

Optional Delay Guarantees Zero Hold Time

XC5200 devices do not have storage elements in the IOBs. However, XC5200 IOBs can be efficiently routed to CLB 7 flip-flops or latches to store the I/O signals.

The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input flip-flop is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperatureor processing-dependent operation.

The input flip-flop setup time is defined between the data measured at the device I/O pin and the clock input at the CLB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the CLB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specified setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement.

When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufficient delay eliminates the possibility of a data hold-time requirement at the external pin. The maximum delay is therefore inserted as the software default.

The XC5200 IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC5200 global clock buffers. (See “Global Lines” on page 96 for a description of the global clock buffers in the XC5200.) For a shorter input register setup time, with

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XC5200 Series Field Programmable Gate Arrays

non-zero hold, attach a NODELAY attribute or property to the flip-flop or input buffer.

IOB Output Signals

Output signals can be optionally inverted within the IOB, and pass directly to the pad. As with the inputs, a CLB flip-flop or latch can be used to store the output signal.

An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB.

The XC5200 devices provide a guaranteed output sink current of 8 mA.

Supported destinations for XC5200-Series device outputs are shown in Table 6.(For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.)

An output can be configured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. (See Figure 12.)

Table 6: Supported Destinations for XC5200-Series Outputs

 

XC5200 Output Mode

Destination

5 V,

CMOS

 

 

 

XC5200 device, VCC=3.3 V,

CMOS-threshold inputs

 

Any typical device, VCC = 3.3 V,

1

CMOS-threshold inputs

some

 

 

 

Any device, VCC = 5 V,

TTL-threshold inputs

 

Any device, VCC = 5 V,

CMOS-threshold inputs

 

1. Only if destination device has 5-V tolerant inputs

OPAD

OBUFT

X6702

Figure 12: Open-Drain Output

Output Slew Rate

The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop.

For XC5200 devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground pin pair. For some XC5200 devices, additional internal Power/Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce.

For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC5200 devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC5200 Series.

XC5200-Series devices have a feature called “Soft Start-up,” designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each IOB.

Global Three-State

A separate Global 3-State line (not shown in Figure 11) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network.

GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to Global Reset. See Figure 8 on page 90 for details. Alternatively, GTS can be driven from any internal node.

Other IOB Options

There are a number of other programmable options in the XC5200-Series IOB.

Pull-up and Pull-down Resistors

Programmable IOB pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls

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XC5200 Series Field Programmable Gate Arrays

to Vcc. The configurable pull-down resistor is an n-channel transistor that pulls to Ground.

The value of these resistors is 20 kΩ − 100 kΩ. This high value makes them unsuitable as wired-AND pull-up resistors.

The pull-up resistors for most user-programmable IOBs are active during the configuration process. See Table 13 on page 124 for a list of pins with pull-ups active before and during configuration.

After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad.

JTAG Support

Embedded logic attached to the IOBs contains test structures compatible with IEEE Standard 1149.1 for boundary scan testing, simplifying board-level testing. More information is provided in “Boundary Scan” on page 98 .

Oscillator

XC5200 devices include an internal oscillator. This oscillator is used to clock the power-on time-out, clear configuration memory, and source CCLK in Master configuration modes. The oscillator runs at a nominal 12 MHz frequency that varies with process, Vcc, and temperature. The output CCLK frequency is selectable as 1 MHz (default), 6 MHz, or 12 MHz.

The XC5200 oscillator divides the internal 12-MHz clock or a user clock. The user then has the choice of dividing by 4, 16, 64, or 256 for the “OSC1” output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” output. The division is specified via a “DIVIDEn_BY=x” attribute on the symbol, where n=1 for OSC1, or n=2 for OSC2. These frequencies can vary by as much as -50% or + 50%.

The OSC5 macro is used where an internal oscillator is required. The CK_DIV macro is applicable when a user clock input is specified (see Figure 13).

OSC1

OSCS

OSC2

OSC1

CK_DIV

OSC2

5200_14

Figure 13: XC5200 Oscillator Macros

VersaBlock Routing

The General Routing Matrix (GRM) connects to the

 

Versa-Block via 24 bidirectional ports (M0-M23). Excluding

 

direct connections, global nets, and 3-statable Longlines,

 

all VersaBlock inputs and outputs connect to the GRM via

 

these 24 ports. Four 3-statable unidirectional signals

 

(TQ0-TQ3) drive out of the VersaBlock directly onto the

 

horizontal and vertical Longlines. Two horizontal global

 

nets and two vertical global nets connect directly to every

 

CLB clock pin; they can connect to other CLB inputs via the

7

GRM. Each CLB also has four unidirectional direct con-

nects to each of its four neighboring CLBs. These direct connects can also feed directly back to the CLB (see Figure 14).

In addition, each CLB has 16 direct inputs, four direct connections from each of the neighboring CLBs. These direct connections provide high-speed local routing that bypasses the GRM.

Local Interconnect Matrix

The Local Interconnect Matrix (LIM) is built from input and output multiplexers. The 13 CLB outputs (12 LC outputs plus a Vcc/GND signal) connect to the eight VersaBlock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. Of the eight VersaBlock outputs, four signals drive each neighboring CLB directly, and provide a direct feedback path to the input multiplexers. The four remaining multiplexer outputs can drive the GRM through four TBUFs (TQ0-TQ3). All eight multiplexer outputs can connect to the GRM through the bidirectional M0-M23 signals. All eight signals also connect to the input multiplexers and are potential inputs to that CLB.

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XC5200 Series Field Programmable Gate Arrays

 

 

 

To GRM

 

 

 

 

 

 

 

 

 

 

M0-M23

 

 

 

 

 

 

 

 

 

 

24

8

 

 

 

 

 

 

Global Nets

4

 

TS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

To

 

 

 

 

 

COUT

 

 

 

 

Longlines

 

 

 

 

 

 

 

 

 

4

 

 

4

 

 

 

 

 

 

and GRM

 

North

 

 

 

 

 

 

 

 

 

 

CLB

 

 

 

 

TQ0-TQ3

 

 

 

 

 

 

 

 

 

 

 

South

4

 

 

 

 

 

 

 

 

 

East

4

 

5

LC3

3

 

 

 

 

 

 

 

 

 

 

 

 

 

West

4

Input

5

 

3

Output

 

 

 

 

Multiplexers

LC2

Multiplexers

 

 

Direct to

 

 

 

 

VCC /GND

8

4

 

 

 

 

 

 

 

 

 

East

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

LC1

3

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

LC0

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Direct North

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

4

Feedback

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

CLR

CIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Direct West

4

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

Direct South

 

 

 

 

 

 

 

X5724

Figure 14: VersaBlock Details

CLB inputs have several possible sources: the 24 signals from the GRM, 16 direct connections from neighboring VersaBlocks, four signals from global, low-skew buffers, and the four signals from the CLB output multiplexers. Unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given CLB input. The flexibility of LUT input swapping and LUT mapping compensates for this limitation. For example, if a 2-input NAND gate is required, it can be mapped into any of the four LUTs, and use any two of the four inputs to the LUT.

Direct Connects

The unidirectional direct-connect segments are connected to the logic input/output pins through the CLB input and output multiplexer arrays, and thus bypass the general routing matrix altogether. These lines increase the routing channel utilization, while simultaneously reducing the delay incurred in speed-critical connections.

The direct connects also provide a high-speed path from the edge CLBs to the VersaRing input/output buffers, and thus reduce pin-to-pin set-up time, clock-to-out, and combinational propagation delay. Direct connects from the input buffers to the CLB DI pin (direct flip-flop input) are only available on the left and right edges of the device. CLB look-up table inputs and combinatorial/registered outputs have direct connects to input/output buffers on all four sides.

The direct connects are ideal for developing customized RPM cells. Using direct connects improves the macro performance, and leaves the other routing channels intact for improved routing. Direct connects can also route through a CLB using one of the four cell-feedthrough paths.

General Routing Matrix

The General Routing Matrix, shown in Figure 15, provides flexible bidirectional connections to the Local Interconnect

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XC5200 Series Field Programmable Gate Arrays

Matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. A pro-

GRM

GRM

GRM

 

 

Versa-

Versa-

Versa-

 

 

Block

Block

Block

 

 

GRM

GRM

GRM

1

 

 

 

Versa-

Versa-

Versa-

 

 

Block

Block

Block

 

 

 

 

 

2

 

GRM

GRM

GRM

 

 

Versa-

Versa-

Versa-

3

 

Block

Block

Block

 

 

 

 

4

7

 

 

 

 

Six Levels of Routing Hierarchy

GRM

4 4

 

1

 

Single-length Lines

 

24

 

2

 

Double-length Lines

 

TS

 

 

 

CLB

 

 

 

 

 

LC3

 

3

 

Direct Connects

 

4

 

 

4

LC2

4

 

 

 

4

 

 

4

LC1

4

 

Longlines and Global Lines

 

 

 

 

 

 

5

LIM

 

 

6 LC0

 

Local Interconnect Matrix

 

 

 

 

 

Logic Cell Feedthrough

 

LIM

5

6

 

 

 

 

 

Path (Contained within each

 

4 4

 

 

 

Logic Cell)

 

 

 

 

 

 

Direct Connects

X4963

Figure 15: XC5200 Interconnect Structure

grammable interconnect point (PIP) establishes an electrical connection between two wire segments. The PIP, consisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirectional) connection between two adjoining wires. A collection of PIPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments. A hierarchy of PIPs and

associated routing segments combine to provide a powerful interconnect hierarchy:

Forty bidirectional single-length segments per CLB provide ten routing channels to each of the four neighboring CLBs in four directions.

Sixteen bidirectional double-length segments per CLB provide four routing channels to each of four other (non-neighboring) CLBs in four directions.

Eight horizontal and eight vertical bidirectional Longline

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XC5200 Series Field Programmable Gate Arrays

segments span the width and height of the chip, respectively.

Two low-skew horizontal and vertical unidirectional glo- bal-line segments span each row and column of the chip, respectively.

Singleand Double-Length Lines

The singleand double-length bidirectional line segments make up the bulk of the routing channels. The dou- ble-length lines hop across every other CLB to reduce the propagation delays in speed-critical nets. Regenerating the signal strength is recommended after traversing three or four such segments. Xilinx place-and-route software automatically connects buffers in the path of the signal as necessary. Singleand double-length lines cannot drive onto Longlines and global lines; Longlines and global lines can, however, drive onto singleand double-length lines. As a general rule, Longline and global-line connections to the general routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix.

Longlines

Longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. Row and column splitter PIPs in the middle of the array effectively double the total number of Longlines by electrically dividing them into two separated half-lines. Longlines are driven by the 3-state buffers in each CLB, and are driven by similar buffers at the periphery of the array from the VersaRing I/O Interface.

Bus-oriented designs are easily implemented by using Longlines in conjunction with the 3-state buffers in the CLB and in the VersaRing. Additionally, weak keeper cells at the periphery retain the last valid logic level on the Longlines when all buffers are in 3-state mode.

Longlines connect to the single-length or double-length lines, or to the logic inside the CLB, through the General Routing Matrix. The only manner in which a Longline can be driven is through the four 3-state buffers; therefore, a Longline-to-Longline or single-line-to-Longline connection through PIPs in the General Routing Matrix is not possible. Again, as a general rule, longand global-line connections to the General Routing Matrix are unidirectional, with the signal direction from these lines toward the routing matrix.

The XC5200 family has no pull-ups on the ends of the Longlines sourced by TBUFs, unlike the XC4000 Series. Consequently, wired functions (i.e., WAND and WORAND) and wide multiplexing functions requiring pull-ups for undefined states (i.e., bus applications) must be implemented in a different way. In the case of the wired functions, the same functionality can be achieved by taking advantage of the

carry/cascade logic described above, implementing a wide logic function in place of the wired function. In the case of 3-state bus applications, the user must insure that all states of the multiplexing function are defined. This process is as simple as adding an additional TBUF to drive the bus High when the previously undefined states are activated.

Global Lines

Global buffers in Xilinx FPGAs are special buffers that drive a dedicated routing network called Global Lines, as shown in Figure 16. This network is intended for high-fanout clocks or other control signals, to maximize speed and minimize skewing while distributing the signal to many loads.

The XC5200 family has a total of four global buffers (BUFG symbol in the library), each with its own dedicated routing channel. Two are distributed vertically and two horizontally throughout the FPGA.

The global lines provide direct input only to the CLB clock pins. The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals.

Four clock input pads at the corners of the chip, as shown in Figure 16, provide a high-speed, low-skew clock network to each of the four global-line buffers. In addition to the dedicated pad, the global lines can be sourced by internal logic. PIPs from several routing channels within the VersaRing can also be configured to drive the global-line buffers.

Details of all the programmable interconnect for a CLB is shown in Figure 17.

GCK1

GCK4

 

GCK2

GCK3

 

 

X5704

Figure 16: Global Lines

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November 5, 1998 (Version 5.2)

XILINX XC5215-5PG299C, XC5215-5HQ240C, XC5215-5HQ208C, XC5215-5BG352C, XC5215-5BG225C Datasheet

R

XC5200 Series Field Programmable Gate Arrays

.

x9010

LONG

 

SINGLE

CARRY

 

DOUBLE

 

GLOBAL

CLB

7

DIRECT

 

 

 

 

 

DIRECT

DIRECT

LONG

GLOBAL

DOUBLE

SINGLE

Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CLB

November 5, 1998 (Version 5.2)

 

 

 

 

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XC5200 Series Field Programmable Gate Arrays

VersaRing Input/Output Interface

The VersaRing, shown in Figure 18, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The VersaRing decouples the core logic from the I/O pads. Each VersaRing Cell provides up to four pad-cell connections on one side, and connects directly to the CLB ports on the other side.

 

 

 

VersaRing

 

8

2

 

 

 

 

 

8

 

8

 

2

2

 

 

2

 

Pad

GRM

10

 

Pad

 

 

 

Interconnect

 

 

4

Pad

 

 

 

 

VersaBlock

4

Pad

 

 

 

 

8

 

8

 

 

 

 

2

 

 

 

2

 

Pad

GRM

10

 

Pad

 

 

 

Interconnect

 

 

4

Pad

 

 

 

 

VersaBlock

4

Pad

 

 

 

 

 

2

 

 

8

2

8

 

 

 

 

 

 

X5705

Figure 18: VersaRing I/O Interface

Boundary Scan

The “bed of nails” has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE boundary scan standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two.

XC5200 devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP can also support two USERCODE instructions. When the boundary scan configuration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output.

Boundary-scan operation is independent of individual IOB configuration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability after configuration provides flexibility for interconnect testing.

Also, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This technique partially compensates for the lack of INTEST support.

The user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices.

The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also discussed in the Xilinx application note XAPP 017: “Boundary Scan in XC4000 and XC5200 Series devices”

Figure 19 on page 99 is a diagram of the XC5200-Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes.

The public boundary-scan instructions are always available prior to configuration. After configuration, the public instructions and any USERCODE instructions are only available if specified in the design. While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period.

In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA device, and to read back the configuration data.

All of the XC4000 boundary-scan modes are supported in the XC5200 family. Three additional outputs for the UserRegister are provided (Reset, Update, and Shift), repre-

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XC5200 Series Field Programmable Gate Arrays

senting the decoding of the corresponding state of the boundary-scan internal state machine.

DATA IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOB

IOB

IOB

IOB

IOB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

BYPASS

IOB

 

 

 

REGISTER

 

M TDO TDI INSTRUCTION REGISTER U

X

M

TDI

U

INSTRUCTION REGISTER

TDO X

 

 

BYPASS

 

IOB

REGISTER

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

IOB

 

IOB

 

IOB

IOB

IOB

IOB

IOB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

sd

D

Q

D

Q

0

 

 

 

 

 

LE

 

 

 

 

1

IOB.O

 

 

0

 

 

 

IOB.T

 

 

0

 

 

 

1

D

Q

 

D

sd

Q

 

1

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LE

 

 

 

 

1

Q

D

sd

Q

 

 

D

 

 

 

0

 

 

 

 

 

 

 

 

LE

 

 

 

 

IOB.I

 

 

 

 

1

 

 

 

 

 

0

 

 

 

 

 

 

 

1

 

 

sd

 

 

 

D

Q

D

 

Q

 

 

0

 

 

 

 

 

 

 

 

LE

 

 

 

 

 

 

 

 

 

1

 

IOB.O

 

 

 

 

0

 

 

 

 

 

 

7

IOB.T

 

 

 

 

0

 

 

 

 

 

 

1

 

 

sd

 

1

 

D

Q

D

 

Q

 

0

 

 

 

 

 

 

 

 

LE

 

 

 

 

 

1

 

 

sd

 

D

Q

D

Q

 

0

 

 

 

 

 

 

LE

 

IOB.I

 

 

 

1

 

 

 

0

 

 

 

 

 

1

 

 

sd

 

D

Q

D

Q

 

0

 

 

 

 

 

 

LE

 

 

 

 

 

0

IOB.O

 

 

 

1

 

 

 

 

DATAOUT

 

UPDATE

EXTEST

SHIFT/

CLOCK DATA

 

 

 

CAPTURE

REGISTER

 

 

 

X1523_01

Figure 19: XC5200-Series Boundary Scan Logic

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

XC5200-Series devices can also be configured through the boundary scan logic. See XAPP 017 for more information.

Data Registers

The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-State pins.

The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals.

The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device.

The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions, USER1 and USER2. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

Instruction Set

The XC5200-Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 7.

Table 7: Boundary Scan Instructions

Instruction I2

Test

TDO Source

I/O Data

I1

 

I0

Selected

Source

 

 

 

 

 

 

 

 

 

 

0

 

0

 

0

EXTEST

DR

DR

 

 

 

 

 

 

 

 

0

 

0

 

1

SAMPLE/PR

DR

Pin/Logic

 

 

 

 

 

ELOAD

 

 

 

 

 

 

 

 

 

 

0

 

1

 

0

USER 1

BSCAN.

User Logic

 

 

 

 

 

 

TDO1

 

 

 

 

 

 

 

 

 

0

 

1

 

1

USER 2

BSCAN.

User Logic

 

 

 

 

 

 

TDO2

 

 

 

 

 

 

 

 

 

1

 

0

 

0

READBACK

Readback

Pin/Logic

 

 

 

 

 

 

Data

 

 

 

 

 

 

 

 

 

1

 

0

 

1

CONFIGURE

DOUT

Disabled

 

 

 

 

 

 

 

 

1

 

1

 

0

Reserved

 

 

 

 

 

 

 

 

1

 

1

 

1

BYPASS

Bypass

 

 

 

 

 

 

Register

 

 

 

 

 

 

 

 

 

Bit Sequence

The bit sequence within each IOB is: 3-State, Out, In. The data-register cells for the TAP pins TMS, TCK, and TDI have an OR-gate that permanently disables the output buffer if boundary-scan operation is selected. Consequently, it is impossible for the outputs in IOBs used by TAP inputs to conflict with TAP operation. TAP data is taken directly from the pin, and cannot be overwritten by injected boundary-scan data.

The primary global clock inputs (PGCK1-PGCK4) are taken directly from the pins, and cannot be overwritten with boundary-scan data. However, if necessary, it is possible to drive the clock input from boundary scan. The external clock source is 3-stated, and the clock net is driven with boundary scan data through the output driver in the clock-pad IOB. If the clock-pad IOBs are used for non-clock signals, the data may be overwritten normally.

Pull-up and pull-down resistors remain active during boundary scan. Before and during configuration, all pins are pulled up. After configuration, the choice of internal pull-up or pull-down resistor must be taken into account when designing test vectors to detect open-circuit PC traces.

From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Table 8. The device-specific pinout tables for the XC5200 Series include the boundary scan locations for each IOB pin.

Table 8: Boundary Scan Bit Sequence

Bit Position

I/O Pad Location

Bit 0 (TDO)

Top-edge I/O pads (right to left)

 

 

Bit 1

...

 

 

...

Left-edge I/O pads (top to bottom)

 

 

...

Bottom-edge I/O pads (left to right)

 

 

...

Right-edge I/O pads (bottom to top)

 

 

Bit N (TDI)

BSCANT.UPD

 

 

BSDL (Boundary Scan Description Language) files for XC5200-Series devices are available on the Xilinx web site in the File Download area.

Including Boundary Scan

If boundary scan is only to be used during configuration, no special elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after configuration.

To indicate that boundary scan remain enabled after configuration, include the BSCAN library symbol and connect pad symbols to the TDI, TMS, TCK and TDO pins, as shown in Figure 20.

7-100

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

 

 

 

Optional

 

 

 

 

 

To User

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IBUF

 

 

 

Logic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BSCAN

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UPDATE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SHIFT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

DRCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

IDLE

 

 

 

To User

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

From

 

 

 

TDO1

 

SEL1

 

 

 

Logic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

User Logic

 

 

 

TDO2

 

SEL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X9000

Figure 20: Boundary Scan Schematic Example

Typically, a 0.1 µF capacitor connected near the Vcc and Ground pins of the package will provide adequate decoupling.

Output buffers capable of driving/sinking the specified 8 mA loads under specified worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions.

Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical.

Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK.

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during configuration. In some applications, a situation may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process.

To prevent activation of boundary scan during configuration, do either of the following:

TMS: Tie High to put the Test Access Port controller in a benign RESET state

TCK: Tie High or Low—do not toggle this clock input.

For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017, “Boundary Scan in XC4000 and XC5200 Devices.“

Power Distribution

Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers, as shown in Figure 21. An independent matrix of Vcc and Ground lines supplies the interior logic of the device.

This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled.

GND

 

Ground and

 

 

Vcc Ring for

 

 

I/O Drivers

 

Vcc

Vcc

 

 

Logic

7

 

Power Grid

 

GND

X5422

 

Figure 21: XC5200-Series Power Distribution

Pin Descriptions

There are three types of pins in the XC5200-Series devices:

Permanently dedicated pins

User I/O pins that can have special functions

Unrestricted user-programmable I/O pins.

Before and during configuration, all outputs not used for the configuration process are 3-stated and pulled high with a 20 kΩ - 100 kΩ pull-up resistor.

After configuration, if an IOB is unused it is configured as an input with a 20 kΩ - 100 kΩ pull-up resistor.

Device pins for XC5200-Series devices are described in Table 9. Pin functions during configuration for each of the seven configuration modes are summarized in “Pin Func-

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

tions During Configuration” on page 124, in the “Configuration Timing” section.

Table 9: Pin Descriptions

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

During

After

 

 

 

 

Pin Name

Config.

Config.

Pin Description

 

 

 

 

 

 

Permanently

Dedicated

Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Five or more (depending on package) connections to the nominal +5 V supply voltage.

 

 

VCC

I

I

All must be connected, and each must be decoupled with a 0.01 - 0.1 µF capacitor to

 

 

 

 

 

 

 

 

 

Ground.

 

 

 

 

 

 

 

 

 

 

 

 

GND

I

I

Four or more (depending on package type) connections to Ground. All must be con-

 

 

nected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-

 

 

 

 

 

 

 

 

 

chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral

 

 

 

 

 

 

 

 

 

mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and

 

 

CCLK

I or O

I

can be selected as the Readback Clock. There is no CCLK High time restriction on

 

 

 

 

 

 

 

 

 

XC5200-Series devices, except during Readback. See “Violating the Maximum High

 

 

 

 

 

 

 

 

 

and Low Time Specification for the Readback Clock” on page 113 for an explanation of

 

 

 

 

 

 

 

 

 

this exception.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it

 

 

 

 

 

 

 

 

 

indicates the completion of the configuration process. As an input, a Low level on

 

 

 

 

 

 

 

 

 

DONE can be configured to delay the global logic initialization and the enabling of out-

 

DONE

I/O

O

puts.

 

 

 

 

 

 

 

 

 

The exact timing, the clock source for the Low-to-High transition, and the optional

 

 

 

 

 

 

 

 

 

pull-up resistor are selected as options in the program that creates the configuration bit-

 

 

 

 

 

 

 

 

 

stream. The resistor is included by default.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-

 

 

 

 

 

 

 

 

 

ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA

 

PROGRAM

I

I

 

executes a complete clear cycle, before it goes into a WAIT state and releases INIT.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The PROGRAM pin has an optional weak pull-up after configuration.

 

 

 

 

User I/O Pins That Can Have Special Functions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During Peripheral mode configuration, this pin indicates when it is appropriate to write

 

 

 

 

 

 

 

 

 

another byte of data into the FPGA. The same status is also available on D7 in Asyn-

 

RDY/BUSY

O

I/O

chronous Peripheral mode, if a read operation is performed when the device is selected.

 

 

 

 

 

 

 

 

 

After configuration, RDY/BUSY is a user-programmable I/O pin.

 

 

 

 

 

 

 

 

 

 

 

RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During Master Parallel configuration, each change on the A0-A17 outputs is preceded

 

 

 

 

 

 

 

O

I/O

by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked

 

RCLK

 

PROMs. It is rarely used during configuration. After configuration, RCLK is a user-pro-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

grammable I/O pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

As Mode inputs, these pins are sampled before the start of configuration to determine

 

 

 

 

 

 

 

 

 

the configuration mode to be used. After configuration, M0, M1, and M2 become us-

M0, M1, M2

I

I/O

er-programmable I/O.

During configuration, these pins have weak pull-up resistors. For the most popular con-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

figuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down

 

 

 

 

 

 

 

 

 

resistor value of 3.3 kΩ is recommended for other modes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,

 

 

 

 

 

 

 

 

 

this pin is a 3-state output, after configuration is completed.

 

 

TDO

O

O

This pin can be user output only when called out by special schematic definitions. To

 

 

 

 

 

 

 

 

 

use this pin, place the library component TDO instead of the usual pad symbol. An out-

 

 

 

 

 

 

 

 

 

put buffer must still be used.

 

 

 

 

 

 

 

 

 

 

 

 

7-102

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Table 9: Pin Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During

After

 

 

 

 

 

 

 

 

 

 

Pin Name

Config.

Config.

 

 

 

Pin Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select

 

 

 

 

 

 

 

 

 

inputs respectively. They come directly from the pads, bypassing the IOBs. These pins

 

 

 

 

 

 

 

 

I/O

can also be used as inputs to the CLB logic after configuration is completed.

 

 

 

TDI, TCK,

 

If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-

 

 

 

I

or I

 

 

 

TMS

ited once configuration is completed, and these pins become user-programmable I/O.

 

 

 

 

(JTAG)

 

 

 

 

 

 

 

 

 

In this case, they must be called out by special schematic definitions. To use these pins,

 

 

 

 

 

 

 

 

 

place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-

 

 

 

 

 

 

 

 

 

put or output buffers must still be used.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High During Configuration (HDC) is driven High until the I/O go active. It is available as

 

 

 

HDC

O

I/O

a control output indicating that configuration is not yet completed. After configuration,

 

 

 

 

 

 

 

 

 

HDC is a user-programmable I/O pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a

 

 

 

 

LDC

O

I/O

control output indicating that configuration is not yet completed. After configuration,

 

 

 

 

 

 

 

 

 

LDC is a user-programmable I/O pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Before and during configuration,

INIT

is a bidirectional signal. A 1 kΩ - 10 kΩ external

 

 

 

 

 

 

 

 

 

pull-up resistor is recommended.

 

 

 

 

 

 

 

 

 

 

 

As an active-Low open-drain output, INIT is held Low during the power stabilization and

 

 

 

 

 

 

 

I/O

I/O

internal clearing of the configuration memory. As an active-Low input, it can be used

 

 

 

 

INIT

 

 

 

 

to hold the FPGA in the internal WAIT state before the start of configuration. Master

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

mode devices stay in a WAIT state an additional 50 to 250 µs after INIT has gone High.

 

 

 

 

 

 

 

 

 

During configuration, a Low on this output indicates that a configuration data error has

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

occurred. After the I/O go active, INIT is a user-programmable I/O pin.

 

 

 

 

 

 

 

 

Four Global inputs each drive a dedicated internal global net with short delay and min-

 

 

 

 

 

 

 

 

 

imal skew. These internal global nets can also be driven from internal logic. If not used

 

 

 

GCK1 -

Weak

I or I/O

to drive a global net, any of these pins is a user-programmable I/O pin.

 

 

 

GCK4

Pull-up

The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input

 

 

 

 

 

 

 

 

 

pad symbol connected directly to the input of a BUFG symbol is automatically placed on

 

 

 

 

 

 

 

 

 

one of these pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These four inputs are used in Asynchronous Peripheral mode. The chip is selected

 

 

 

 

 

 

 

 

 

when

CS0

is Low and CS1 is High. While the chip is selected, a Low on Write Strobe

 

 

 

 

 

 

 

 

 

(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low

 

 

CS0, CS1,

I

I/O

on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —

 

 

 

WS, RS

and drives D0 - D6 High.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.

 

 

 

 

 

 

 

 

 

WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write

 

 

 

 

 

 

 

 

 

Strobe overrides. After configuration, these are user-programmable I/O pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

A0 - A17

O

I/O

During Master Parallel configuration, these 18 output pins address the configuration

 

 

 

EPROM. After configuration, they are user-programmable I/O pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D0 - D7

I

I/O

During Master Parallel, Peripheral, and Express configuration, these eight input pins re-

 

 

 

ceive configuration data. After configuration, they are user-programmable I/O pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During Slave Serial or Master Serial configuration, DIN is the serial configuration data

 

 

 

 

DIN

I

I/O

input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is

 

 

 

 

 

 

 

 

 

the D0 input. After configuration, DIN is a user-programmable I/O pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During configuration in any mode but Express mode, DOUT is the serial configuration

 

 

 

 

 

 

 

 

 

data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes

 

 

 

 

 

 

 

 

 

on the falling edge of CCLK.

 

 

 

DOUT

O

I/O

In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained

 

 

 

 

 

 

 

 

 

FPGAs, to enable and disable downstream devices.

 

 

 

 

 

 

 

 

 

After configuration, DOUT is a user-programmable I/O pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

November 5, 1998 (Version 5.2)

7-103

 

 

R

XC5200 Series Field Programmable Gate Arrays

Table 9: Pin Descriptions (Continued)

 

I/O

I/O

 

 

During

After

 

Pin Name

Config.

Config.

Pin Description

 

 

 

 

Unrestricted User-Programmable I/O Pins

 

 

 

 

 

Weak

 

These pins can be configured to be input and/or output after configuration is completed.

I/O

I/O

Before configuration is completed, these pins have an internal high-value pull-up resis-

Pull-up

 

 

tor (20 kΩ - 100 kΩ) that defines the logic level as High.

 

 

 

 

 

 

 

Configuration

Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC5200-Series devices use several hundred bits of configuration data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The development system translates the design into a netlist file. It automatically partitions, places and routes the logic and generates the configuration data in PROM format.

Special Purpose Pins

Three configuration mode pins (M2, M1, M0) are sampled prior to configuration to determine the configuration mode. After configuration, these pins can be used as auxiliary I/O connections. The development system does not use these resources unless they are explicitly specified in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of the input or output pad symbol.

In XC5200-Series devices, the mode pins have weak pull-up resistors during configuration. With all three mode pins High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common configuration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 kΩ.) After configuration, these pins can individually have weak pull-up or pull-down resistors, as specified in the design. A pull-down resistor value of 3.3kΩ is recommended.

These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of M0/RT, M1/RD is desired.

Configuration Modes

XC5200 devices have seven configuration modes. These modes are selected by a 3-bit input code applied to the M2,

M1, and M0 inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode,

Table 10: Configuration Modes

Mode

M2

M1

M0

CCLK

Data

 

 

 

 

 

 

Master Serial

0

0

0

output

Bit-Serial

 

 

 

 

 

 

Slave Serial

1

1

1

input

Bit-Serial

 

 

 

 

 

 

Master

1

0

0

output

Byte-Wide,

Parallel Up

 

 

 

 

increment

 

 

 

 

 

from 00000

 

 

 

 

 

 

Master

1

1

0

output

Byte-Wide,

Parallel Down

 

 

 

 

decrement

 

 

 

 

 

from 3FFFF

 

 

 

 

 

 

Peripheral

0

1

1

input

Byte-Wide

Synchronous*

 

 

 

 

 

 

 

 

 

 

 

Peripheral

1

0

1

output

Byte-Wide

Asynchronous

 

 

 

 

 

 

 

 

 

 

 

Express

0

1

0

input

Byte-Wide

 

 

 

 

 

 

Reserved

0

0

1

 

 

 

 

 

 

Note :*Peripheral Synchronous can be considered byte-wide Slave Parallel

which is used primarily for daisy-chained devices. The seventh mode, called Express mode, is an additional slave mode that allows high-speed parallel configuration. The coding for mode selection is shown in Table 10.

Note that the smallest package, VQ64, only supports the Master Serial, Slave Serial, and Express modes.A detailed description of each configuration mode, with timing information, is included later in this data sheet. During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during configuration are shown in Table 13 on page 124.

Master Modes

The three Master modes use an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slave devices. They also generate address and timing for external PROM(s) containing the configuration data.

Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, for compatibility with different microprocessor addressing conventions. The

7-104

November 5, 1998 (Version 5.2)

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