R
XC3000 Series Field Programmable Gate Arrays
7-8 November 9, 1998 (Version 3.1)
The input-buffer portion of each IOB provides threshold
detection to translate external signals applied to the pack-
age pin to internal logic levels. The global input-buffer
threshold of th e IOBs can be programme d to be compat ible
with either TTL or CMOS levels . The buffered input sign al
drives the data input of a storage element, which may be
configured as either a flip-flop or a latch. The clocking
polarity (rising/falling edge-triggered flip-flop, High/Low
transparent latch) is programmable for each of the two
clock lines on each of the four die edges. Note that a clock
line driving a
rising
edge-triggered f l ip- flo p mak es any l a tch
driven by the sa me line on the same edge Low-level trans-
parent and vice vers a (
falling
edge,
High
transparent). All
Xilinx primitives in the supported schematic-entry pack-
ages, however, are positive edge-triggered flip-flops or
High transparent latches. When one clock line m ust drive
flip-flops as well as latch es, it is nec essary to c ompensa te
for the difference in clocking polarities with an additional
inverter either in the flip-flop clock input or the latch-enable
input. I/O storage elements are reset during configuration
or by the active-Low chip RESET
input. Both direct inp ut
(from IOB pi n I) a nd regi stered input (from IOB pi n Q) s ig-
nals are available for interconnect.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can p roduce add itional pow er dissip ation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user IOB includes a
programmable high-impedance pull-up resistor, which may
be selected by the pro gram to prov ide a consta nt High for
otherwise undriven package pins. Although the Field Pro-
grammable Gate Array provides circuitry to provide input
protection for electrostatic discharge, normal CMOS han-
dling precautions should be observed.
Flip-flop loop delay s for the IOB and logic-bloc k flip-flops
are short, providing good performance under asynchro-
nous clock and dat a conditi ons. Shor t loop del ays minimi ze
the probability of a metastable condition that can result
from assertion of the clock during data transitions. Because
of the short-loop -de lay ch arac terist ic in th e Fie ld Pr ogr am-
mable Gate Ar ray, the IOB flip-flops can be used to syn-
chronize external signals applied to the device. Once
synchronized in the IOB, the signals can be used internally
without further consideration of their clock relative timing,
except as it applies to the internal logic and routing-path
delays.
IOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTL- com-
patible signal levels (8 mA in the XC3100A family ). The net-
work driving IOB pin O becomes the registered or direct
data source for the output buffer. The 3-state control signal
(IOB) pin T can control output activity. An open-drain output
may be obtained by using the same signal for driving the
output and 3-state signal nets so that the buffer output is
enabled only for a Low.
Configuration pr ogram bits for each IOB control featu res
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 4 control
the following options.
• Logic inversion of the output is controlled by one
configuration program bit per IOB.
• Logic 3-state control of each IOB output buffer is
determined by the states of configuration progr am bits
that turn the bu ffer on, or off, or select the output buffer
3-state control interconnection (IOB pin T). When this
IOB output con tr ol s ign al i s Hig h, a l og ic o ne, t he buf f er
is disabled and the package pin is hig h impedance.
When this IOB outp ut contr ol signa l is Low, a logic ze ro,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense
(output enable) is controlled by an additional
configuration program bit.
• Direct or registered output is selectable for each IOB.
The register us es a posit ive-e dge, clo cked f lip- flo p. The
clock source may be supplied (IOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
• Increased output transition s peed can be selected to
improve critical timing. Slower transiti ons reduce
capacitive-load peak currents of non-critical outputs
and minimize system noise.
• An internal high-impedance pull-up resistor (active by
default) prevents unconnected inputs from floating.
Unlike the original XC3000 series, the XC3000A,
XC3000L, XC3100A, and XC3100L families include the
Soft Startup feature. When the configuration process is fin-
ished and the device starts up in user mode, the first activa-
tion of the o utputs is automa tically slew-rate lim ited. This
feature avoids potential ground bounce when all outputs
are turned on sim ultaneously. After start-up, the sle w rate
of the individual outputs is determined by the individual
configuration option.
Summary of I/O Options
• Inputs
-Direct
- Flip-flop/latch
- CMOS/TTL threshold (chip inputs)
- Pull-up resistor/open circui t
• Outputs
- Direct/regi stered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable (inverse)