XILINX XC2S50-6TQ144C, XC2S50-6PQ208C, XC2S50-6FG256C, XC2S50-5TQ144I, XC2S50-5TQ144C Datasheet

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Spartan-II 2.5V FPGA Family:

Introduction and Ordering

Information

DS001-1 (v2.3) November 1, 2001

Preliminary Product Specification

 

 

Introduction

The Spartan™-II 2.5V Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz.

Spartan-II devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined Virtex-based architecture. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.

The Spartan-II family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Features

Second generation ASIC replacement technology

-Densities as high as 5,292 logic cells with up to 200,000 system gates

-Streamlined features based on Virtex architecture

-Unlimited reprogrammability

-Very low cost

Table 1: Spartan-II FPGA Family Members

System level features

-SelectRAM+™ hierarchical memory:

·16 bits/LUT distributed RAM

·Configurable 4K bit block RAM

·Fast interfaces to external RAM

-Fully PCI compliant

-Low-power segmented routing architecture

-Full readback ability for verification/observability

-Dedicated carry logic for high-speed arithmetic

-Dedicated multiplier support

-Cascade chain for wide-input functions

-Abundant registers/latches with enable, set, reset

-Four dedicated DLLs for advanced clock control

-Four primary low-skew global clock distribution nets

-IEEE 1149.1 compatible boundary scan logic

Versatile I/O and packaging

-Low cost packages available in all densities

-Family footprint compatibility in common packages

-16 high-performance interface standards

-Hot swap Compact PCI friendly

-Zero hold time simplifies system timing

Fully supported by powerful Xilinx development system

-Foundation ISE Series: Fully integrated software

-Alliance Series: For use with third-party tools

-Fully automatic mapping, placement, and routing

 

 

 

CLB

 

Maximum

Total

Total

 

Logic

System Gates

Array

Total

Available

Distributed RAM

Block RAM

Device

Cells

(Logic and RAM)

(R x C)

CLBs

User I/O(1)

Bits

Bits

XC2S15

432

15,000

8 x 12

96

86

6,144

16K

 

 

 

 

 

 

 

 

XC2S30

972

30,000

12 x 18

216

132

13,824

24K

 

 

 

 

 

 

 

 

XC2S50

1,728

50,000

16 x 24

384

176

24,576

32K

 

 

 

 

 

 

 

 

XC2S100

2,700

100,000

20 x 30

600

196

38,400

40K

 

 

 

 

 

 

 

 

XC2S150

3,888

150,000

24 x 36

864

260

55,296

48K

 

 

 

 

 

 

 

 

XC2S200

5,292

200,000

28 x 42

1,176

284

75,264

56K

 

 

 

 

 

 

 

 

Notes:

1.All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS001-1 (v2.3) November 1, 2001

www.xilinx.com

1

Preliminary Product Specification

1-800-255-7778

 

XILINX XC2S50-6TQ144C, XC2S50-6PQ208C, XC2S50-6FG256C, XC2S50-5TQ144I, XC2S50-5TQ144C Datasheet

Spartan-II 2.5V FPGA Family: Introduction and Ordering Information

R

General Overview

The Spartan-II family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1).

Spartan-II FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes.

Spartan-II FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-II FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production.

Spartan-II FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-II devices provide system clock rates up to 200 MHz. Spartan-II FPGAs offer the most cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-II FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features.

The Xilinx XC17S00A PROM family is recommended for serial configuration of Spartan-II FPGAs. The In-System Programmable (ISP) XC18V00 PROM family is recommended for parallel or serial configuration.

DLL

BLOCK RAM

BLOCK RAM

CLBs CLBs

CLBs CLBs

DLL

BLOCK RAM

BLOCK RAM

 

DLL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DLL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XC2S15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS001_01_091800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1: Basic Spartan-II Family FPGA Block Diagram

2

www.xilinx.com

DS001-1 (v2.3) November 1, 2001

 

1-800-255-7778

Preliminary Product Specification

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