XILINX XC2C64-7VQ44I, XC2C64-7VQ44C, XC2C64-7VQ100I, XC2C64-7VQ100C, XC2C64-7PC44I Datasheet

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XC2C64 CoolRunner-II CPLD

DS092 (v1.0) January 3, 2002	Advance Product Specification

Features

•Optimized for 1.8V systems

-Industry’s fastest low power CPLD

-Static Icc of less than 100 microamps at all times

-Densities from 32 to 512 macrocells

•Industry’s best 0.18 micron CMOS CPLD

-Optimized architecture for effective logic synthesis

-Multi-voltage I/O operation — 1.5V to 3.3V

•Available in multiple package options

-44-pin PLCC with 33 user I/O

-44-pin VQFP with 33 user I/O

-56-ball CP (0.05mm) BGA with 45 user I/O

-100-pin VQFP with 64 user I/O

•Advanced system features

-Fastest in system programming

·1.8V ISP using IEEE 1532 (JTAG) interface

-IEEE1149.1 JTAG Boundary Scan Test

-Optional Schmitt trigger input (per pin)

-Unsurpassed low power management

-FZP 100% CMOS product term generation

-Flexible clocking modes

·Optional DualEDGE triggered registers

-Global signal options with macrocell control

·Multiple global clocks with phase selection per macrocell

·Multiple global output enables

·Global set/reset

-Abundant product term clocks, output enables and set/resets

-Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks

-Advanced design security

-Open-drain output option for Wired-OR and LED drive

-Optional bus-hold or weak pullup on selected I/O pins

-Optional configurable grounds on unused I/Os

-Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts

-PLA architecture

·Superior pinout retention

·100% product term routability across function block

-Hot pluggable

-Design entry/verification using Xilinx and industry standard CAE tools

-Free software support for all densities using Xilinx

WebPACK™ or WebFITTER™ tools

-Industry leading nonvolatile 0.18 micron CMOS process

-Guaranteed 1,000 program/erase cycles

-Guaranteed 20 year data retention

Refer to the CoolRunner™ -II family data sheet for architecture description.

Description

The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved

This device consists of four Function Blocks inter-con- nected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output control signals include slew rate control, bus hold and open drain. A Schmitt trigger input is available on a per input pin basis. In addition to combinatorial and registered outputs, the registers may be configured as fast inputs.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. These clocks are additionally used to set or preset individual macrocell registers on power up. Local clocks are generated in specific Function Blocks and only available to macrocell registers in that Function Block.

A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows performance where it is needed without raising the total power consumption of the entire device.

The CoolRunner-II 64-macrocell CPLD is I/O compatible with standard LVTTL33 and LVCMOS18, 25, and 33 volts (see Table 1). This device is also 1.5 volt I/O compatible with the use of Schmitt inputs.

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XC2C64 CoolRunner-II CPLD

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Fast Zero Power Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ Fast Zero Power™ (FZP), a design technique that makes use of CMOS technology in both the fabrication and design methodology. FZP design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.

Supported I/O Standards

The CoolRunner-II 64 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose

EIA/JESDSA standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt inputs.

Table 1: I/O Standards for XC2C64

				Board
I/O	Output	Input	Input	Termination
Standard	VCCIO	VCCIO	VREF	Voltage VT
LVTTL	3.3V	3.3V	N/A	N/A
LVCMOS33	3.3	3.3	N/A	N/A
LVCMOS25	2.5	2.5	N/A	N/A
LVCMOS18	1.8	1.8	N/A	N/A

ICC (mA)

25

20

15

10

5

0

0

50

100

150

200

250

300

Frequency (MHz)

															DS092_07_121501
							Figure 1: ICC vs Frequency
Table 2: I	CC	vs Frequency (LVCMOS 1.8V T							= 25°C)(1)
						A
											Frequency (MHz)
				50	75	100			125		150	175		200	225	250	275	300
Typical ICC (mA)				3.6	5.5	7.3			9.1		10.8	12.5		14.2	15.9	17.5	19.2	20.8

Notes:

1.16-bit up/down, resettable binary counter (one counter per function block).

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XC2C64 CoolRunner-II CPLD

Absolute Maximum Ratings

Symbol	Description	Value	Units
VCC	Supply voltage relative to ground	–0.5 to 2.0	V
VCCIO	Supply voltage for output drivers	–0.5 to 4.0	V
VIN	Input voltage relative to ground(1)	–0.5 to 4.0	V
VTS	Voltage applied to 3-state output(1)	–0.5 to 4.0	V
VSTG	Storage Temperature (ambient)	–65 to +150	°C
TSOL	Maximum Soldering temperature (10s @ 1/16in. = 1.5mm)	+ 60	°C
TJ	Junction Temperature	+ 50	°C

Notes:

1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

Recommended Operating Conditions

Symbol		Parameter			Min	Max	Units
VCC		Supply voltage for internal logic		Commercial TA = 0°C to +70°C	1.7	1.9	V
		and input buffers
				Industrial TA = –40°C to +85°C	1.7	1.9	V
VCCIO		Supply voltage for output drivers @ 3.3V operation			3.0	3.6	V
		Supply voltage for output drivers @ 2.5V operation			2.3	2.7	V
		Supply voltage for output drivers @ 1.8V operation			1.7	1.9	V
		Supply voltage for output drivers @ 1.5V operation(1)			1.4	1.6	V

Notes:

1.Use input hysteresis for 1.5V LVCMOS.

DC Electrical Characteristics (Over Recommended Operating Conditions)

Symbol	Parameter	Test Conditions	Min.	Max.	Units
ICCSB	Standby current	VCC = 1.9V, VCCIO = 3.6V		100	A
ICC	Dynamic current	f = 1 MHz			mA
		f = 50 MHz			mA
CJTAG	JTAG input capacitance	f = 1 MHz			pF
CCLK	Global clock input capacitance	f = 1 MHz			pF
CIO	I/O capacitance	f = 1 MHz			pF

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LVCMOS 3.3V DC Voltage Specifications

Symbol	Parameter	Test Conditions	Min.	Max.	Units
VCCIO	Input source voltage		3.0	3.6	V
VIH	High level input voltage		2	VCCIO + 0.3V	V
VIL	Low level input voltage		–0.3	0.8	V
VOH	High level output voltage	IOH = –8 mA, VCCIO = 3V	VCCIO – 0.4V	-	V
		IOH = –0.1 mA, VCCIO = 3V	VCCIO – 0.2V	-	V
VOL	Low level output voltage	IOL = 8 mA, VCCIO = 3V	-	0.4	V
		IOL = 0.1 mA, VCCIO = 3V	-	0.2	V
IIL	Input leakage current	VIN = 0V or VCCIO to 3.9V	–10	10	A
IIH	I/O High-Z leakage	VIN = 0V or VCCIO to 3.9V	–10	10	A
CJTAG	JTAG input capacitance	f = 1 MHz			pF
CCLK	Global clock input capacitance	f = 1 MHz			pF
CIO	I/O capacitance	f = 1 MHz			pF
LVCMOS 2.5V DC Voltage Specifications

Symbol	Parameter		Test Conditions	Min.	Max.	Units
VCCIO	Input source voltage			2.3	2.7	V
VIH	High level input voltage			1.7	3.9	V
VIL	Low level input voltage			–0.3	0.7	V
VOH	High level output voltage		IOH = –8 mA, VCCIO = 3V	VCCIO – 0.4V	-	V
			IOH = –0.1 mA, VCCIO = 3V	VCCIO – 0.2V	-	V
VOL	Low level output voltage		IOL = 8 mA, VCCIO = 3V	-	0.4	V
			IOL = 0.1mA, VCCIO = 3V	-	0.2	V
IIL	Input leakage current		VIN = 0V or VCCIO to 3.9V	–10	10	A
IIH	I/O High-Z leakage		VIN = 0V or VCCIO to 3.9V	–10	10	A
CJTAG	JTAG input capacitance		f = 1 MHz			pF
CCLK	Global clock input capacitance		f = 1 MHz			pF
CIO	I/O capacitance		f = 1 MHz			pF

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