Xilinx VCU1525 User Manual

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VCU1525

Reconfigurable

Acceleration Platform

User Guide

UG1268 (v1.5) March 22, 2019

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

03/22/2019

1.5

Removed references to PCIe Gen4. Updated graphics to remove schematic detail.

 

 

Updated QSFP28 Module Connectors. Updated and moved Appendix A Board

 

 

Installation into Chapter 3, Board and Deployment Software Installation. Updated

 

 

Markings in Appendix A, Regulatory and Compliance Information.

 

 

 

09/27/2018

1.4

Added the Electrostatic Discharge Caution section. Renamed heading QSFP28 Module

 

 

Connectors and updated the section (28 Gb/s QSFP+ became QSFP28 throughout).

 

 

Updated banks in Figure 3-1. Renamed Figure 3-1. Updated DDR4 DIMM Memory.

 

 

Note: Figure numbers are accurate as of version 1.4.

 

 

 

08/07/2018

1.3

Revised Step 4: Program the Base Platform.

 

 

Note: This citation was accurate as of version 1.3.

 

 

 

07/09/2018

1.2

Revised Board Features, Board Specifications, Table 2-1, VCU1525 Board Installation,

 

 

and Figure 3-1. Removed Xilinx constraints file information. Added , Board and

 

 

Deployment Software Installation.

 

 

Note: Table and figure numbers are accurate as of version 1.2.

 

 

 

04/02/2018

1.1

Revised Board Specifications and VCU1525 Board Installation. Updated Table 2-1,

 

 

Table 2-2, and Table 3-2. Revised paragraph after Table 3-1. Added Figure 3-2.

 

 

Updated Figure 3-3, Figure 3-4, and Figure 3-1. Revised Appendix A, Regulatory and

 

 

Compliance Information.

 

 

Note: Table and figure numbers are accurate as of version 1.1.

 

 

 

11/13/2017

1.0

Initial Xilinx release.

 

 

 

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Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2: Board Component Descriptions

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Virtex UltraScale+ XCVU9P-L2FSGD2104E FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

DDR4 DIMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Quad SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

USB JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

FT4232HQ USB-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PCI Express Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

QSFP28 Module Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

VCU1525 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Chapter 3: Board and Deployment Software Installation

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Safety and Antistatic Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Electrostatic Discharge Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Step 1: Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Step 2: Deployment Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

XRT and Deployment Shell Installation Procedures on RedHat and CentOS . . . . . . . . . . . . . . . . . . . . . . . . . .18 XRT and Deployment Shell Installation Procedures on Ubuntu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Step 3: Board Bring-Up and Validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Running lspci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Running xbutil flash scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Running xbutil validate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

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Step 4: Installing the Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Generating the xbutil flash Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Appendix A: Regulatory and Compliance Information

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Appendix B: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Xilinx VCU1525 User Manual

Chapter 1

Introduction

Overview

The VCU1525 Reconfigurable Acceleration Platform is a peripheral component interconnect express (PCIe®) Gen3 x16 compliant board featuring the Xilinx® Virtex® UltraScale+™ XCVU9P-L2FSGD2104E FPGA. This Xilinx FPGA-based PCIe accelerator board is designed to accelerate compute-intensive applications like machine learning, data analytics, and video processing.

The VCU1525 board is available in both active and passive cooling configurations and designed to be used in cloud data center servers.

Figure 1-1 shows the VCU1525 active cooling configuration (PC applications).

X20017-110217

Figure 1-1: VCU1525 Reconfigurable Acceleration Platform (Active Cooling)

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Chapter 1: Introduction

Figure 1-2 shows the VCU1525 passive cooling configuration (data center server applications).

X20018-110217

Figure 1-2: VCU1525 Reconfigurable Acceleration Platform (Passive Cooling)

CAUTION! The VCU1525 board with passive cooling is designed to be installed into a data center server, where controlled air flow provides direct cooling. The VCU1525 board with active cooling is designed to be installed into a PC environment where the air flow is uncontrolled, hence this configuration has the heat sink and fan enclosure cover installed to provide appropriate cooling. In either cooling configuration, the board enclosure makes the board top-side components inaccessible (except the triple-LED module DS3 which protrudes through the left front end PCIe bracket). Board details revealed in this user guide are provided to aid understanding of board features. If the cooling enclosure is removed from either configuration of the board and it is powered-up, external fan cooling airflow MUST be applied to prevent over-temperature shut-down and possible damage to the board electronics.

See Appendix B, Additional Resources and Legal Notices for references to documents, files, and resources relevant to the VCU1525 board.

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Chapter 1: Introduction

Block Diagram

A block diagram of the VCU1525 board is shown in Figure 1-3.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

244-pin DIMM interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64-bit + ECC dual rank support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x4/x8 UDIMM support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C0

PC4-2400 compatible

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clocks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

244-pin DIMM interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64-bit + ECC dual rank support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x4/x8 UDIMM support

 

 

 

 

XADC

 

 

 

 

 

 

 

 

 

 

C2

PC4-2400 compatible

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

244-pin DIMM interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEDs

 

 

 

 

 

 

 

 

 

 

 

64-bit + ECC dual rank support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x4/x8 UDIMM support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VU9P

 

 

 

 

 

C3

PC4-2400 compatible

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QSFP #2

 

 

 

D2104

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

244-pin DIMM interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64-bit + ECC dual rank support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x4/x8 UDIMM support

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QSFP #1

 

 

 

 

 

 

 

 

 

 

 

C1

PC4-2400 compatible

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QSPI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIP SW

 

POWER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCIe GEN1/2/3 x 1/2/4/8/16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X19964-022419

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1-3: VCU1525 Board Block Diagram

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Chapter 1: Introduction

Board Features

The VCU1525 board features are listed in this section. Detailed information for each feature is provided in Feature Descriptions in Chapter 2.

Virtex UltraScale+ XCVU9P-L2FSGD2104E FPGA

Memory (four independent dual-rank DDR4 interfaces)

°64 gigabyte (GB) DDR4 memory

°4x DDR4 16 GB, 2400 mega-transfers per second (MT/s), 64-bit with error correcting code (ECC) DIMM

°x4/x8 unregistered dual inline memory module (RDIMM) support

Configuration options

°1 gigabit (Gb) Quad Serial Peripheral Interface (SPI) flash memory

°Micro-AB universal serial bus (USB) JTAG configuration port

16-lane PCI Express

Two QSFP28 100G interfaces

USB-to-UART FT4232HQ bridge with Micro-AB USB connector

Integrated Endpoint block for PCI Express connectivity

°Gen1, 2 or 3 x1/x2/x4/x8/x16

I2C bus

Status LEDs

Power management with system management bus (SMBus) voltage, current, and temperature monitoring

Dynamic power sourcing based on external power supplied

75W PCIe slot functional with 35 A max VCCINT current PCIe slot power only

150 W PCIe slot functional with 110 A max VCCINT current PCIe slot power and 6-pin PCIe Aux power cable connected

225 W PCIe slot functional with 160 A max VCCINT current PCIe slot power and 8-pin PCIe Aux power cable connected

Two QSFP28 100G interfaces

Onboard reprogrammable flash configuration memory

Front panel JTAG and universal asynchronous receiver-transmitter (UART) access through the USB port

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Chapter 1: Introduction

FPGA configurable over USB/JTAG and Quad SPI configuration flash memory

Thermal management with variable rate fan for minimal fan noise (active version)

Board Specifications

Dimensions

Height: 4.2 inch (10.67 cm)

PCB thickness (±5%): 0.062 inch (0.157 cm)

Board length, passive heat sink: 9.2 inch (23.4 cm)

Board length, active heat sink: 11.4 inch (29 cm)

Board thickness with heat sink enclosure installed:

°Active: 1.52 inch (3.86 cm)

°Passive: 1.44 inch (3.66 cm)

Dual slot PCIe full-length, full height form-factor compliant

Note: A 3D model of this board is not available.

Environmental

Temperature

Operating: 0°C to +45°C

Storage: –25°C to +60°C

Humidity

10% to 90% non-condensing

Operating Voltage

PCIe slot +12 VDC, +3.3 VDC, +3.3 VAUXDC, External +12 VDC

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Chapter 1: Introduction

FPGA Configuration

The VCU1525 board supports two UltraScale+ FPGA configuration modes:

Quad SPI flash memory

JTAG using USB JTAG configuration port lower connector in the PCIe bracket

The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 Master SPI mode with pull-up/down resistors.

At power up, the FPGA is configured by the Quad SPI NOR Flash device (Micron MT25QU01GBBA8E12-0SIT) with the FPGA_CCLK operating at clock rate of 105 MHz (EMCCLK) using the Master Serial Configuration mode.

The Quad SPI flash memory NOR device has a capacity of 1 Gb.

While the FPGA default mode selects Quad SPI configuration, JTAG mode overrides it if invoked. JTAG mode is always available independent of the Mode pin settings.

For complete details on configuring the FPGA, see UltraScale Architecture Configuration User Guide (UG570) [Ref 1].

Table 1-1: Configuration Modes

Configuration Mode

M[2:0]

Bus Width

CCLKL Direction

Master SPI

001

x1, x2, x4

FPGA output

 

 

 

 

JTAG

Not applicable - JTAG overrides

x1

Not applicable

 

 

 

 

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