Xilinx LogiCore PCI v3.0 User Manual

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LogiCORE™ PCI v3.0

Getting Started Guide

UG157 August 31, 2005 v3.0.151

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Xilinx LogiCore PCI v3.0 User Manual

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Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of this Specification may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Specification; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification.

THE SPECIFICATION IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE SPECIFICATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRDPARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICATION, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE SPECIFICATION, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE SPECIFICATION. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE SPECIFICATION TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Specification is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Specification in such High-Risk Applications is fully at your risk.

© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

PCI v3.0.151 Getting Started Guide

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The following table shows the revision history for this document.

 

Version

Revision

 

 

 

06/01/00

1.0

Initial Xilinx release.

 

 

 

06/15/00

1.1

Accumulated miscellaneous updates and bug fixes.

 

 

 

07/26/00

1.2

Accumulated miscellaneous updates and bug fixes.

 

 

 

08/28/00

1.3

Fine tuning of text frame and paragraph format spacings.

 

 

 

04/11/01

2.0

Revised formats to take advantage of FrameMaker 6.0 book features.

 

 

 

05/02/01

2.1

Master page changes.

 

 

 

07/11/01

2.2

Accumulated miscellaneous updates and bug fixes.

 

 

 

04/04/02

2.2.1

Updated trademarks page in ug000_title.fm.

 

 

 

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Version

Revision

 

 

 

06/24/02

3.0

Initial Xilinx release of corporate-wide common template set, used for User Guides,

 

 

Tutorials, Release Notes, Manuals, and other lengthy, multiple-chapter documents

 

 

created by both CMP and ITP. See related documents for further information.

 

 

Descriptions for revisions prior to v3.0 have been abbreviated. For a full summary of revision

 

 

changes prior to v3.0, refer to v2.2.1 template set.

 

 

 

10/30/02

3.1

Updated spelling of RocketIO and SelectIO trademarks in ug000_title.fm per 10/09/02

 

 

broadcast email announcement. Also updated file version number and date.

 

 

 

12/06/02

3.2

Fixed all instances of old character formats in header/footer in Master pages.

 

 

 

01/20/03

3.3

Revised copyright date in ug000_title.fm to 2003. Changed all instances of “Manual” in

 

 

ug000_preface.fm to “Guide”. Added PDF Information format under Format

 

 

Document PDF Setup...

 

 

 

02/06/03

3.4

Added paragraph formats GlossBulleted, GlossNumbered, and GlossNumberedCont.

 

 

 

02/25/03

3.4.1

Minor clean-ups and corrections.

 

 

 

03/25/03

3.5

Corrected Reference Page identification problem that prevented the IX (index)

 

 

Reference page from taking control of Index formatting.

 

 

Modified paragraph tags Level1IX through Level3IX (index entries) to provide a

 

 

more uniform appearance and enhance clarity.

 

 

Removed <Italic> attribute from Heading2TOC special string on Reference pages.

 

 

Changed autonumbering properties of FigureTitle and TableTitle to remove chapter

 

 

number and hyphen.

 

 

 

04/30/03

3.5.1

Updated Additional Resources table in Preface to give correct URL to data sheets index

 

 

page instead of to obsolete Programmable Logic Data Book page.

 

 

 

11/11/04

3.5.2

Added installation and licensing chapter; updated to current template.

 

 

 

12/01/04

3.6

Updated to include Virtex-4 information.

 

 

 

3/7/05

3.7

Updated to ISE 7.1i and build number 3.0.145.

 

 

 

5/13/05

4.0

Updated to build 3.0.150 and Xilinx tools 7.1i SP2.

 

 

 

8/31/05

5.0

Updated to build 3.0.151 and Xilinx tools 7.1i SP4.

 

 

 

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Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1: Getting Started

About the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCI Interface Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: Installing and Licensing the Core

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Installing the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CORE Generator IP Updates Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Manual Installation: CORE Generator IP Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Direct Download of Standalone Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Licensing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Direct Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Installing Your License File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 3: Family Specific Considerations

Design Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Bus Width Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Datapath Output Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Input Delay Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Regional Clock Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Bus Clock Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Generating Bitstreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Chapter 4: Functional Simulation

 

Cadence NC-Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

Model Technology ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Chapter 5: Synthesizing a Design

Synplicity Synplify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Exemplar LeonardoSpectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Xilinx XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 6: Implementing a Design

 

ISE Foundation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

Chapter 7: Timing Simulation

 

Cadence NC-Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55

Model Technology ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

56

Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

56

VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Preface

About This Guide

The PCI Getting Started Guide provides information about the LogiCORE™ Peripheral Component Interconnect (PCI) interface, which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions.

This guide discusses the supported design flows for 32-bit and 64-bit PCI interfaces based on the Virtex™ and Spartan™ architectures, and provides an example design in both Verilog-HDL and VHDL.

Guide Contents

This manual contains the following chapters:

Chapter 1, “Getting Started” describes the core and related information, including additional resources, technical support, and submitting feedback to Xilinx.

Chapter 2, “Installing and Licensing the Core” provides information about installing and licensing the core.

Chapter 3, “Family Specific Considerations” provides information about design considerations specific to the PCI interface targeting Virtex and Spartan devices.

Chapter 4, “Functional Simulation” describes how to simulate the example design using the supported functional simulation tools, including Cadence NC-Verilog v5.0 and Model Technology ModelSim v5.7b.

Chapter 5, “Synthesizing a Design” how to synthesize the example design using the supported synthesis tools, including Synplicity Synplify v7.3, Exemplar LeonardoSpectrum v2003a, and Xilinx XST.

Chapter 6, “Implementing a Design” describes how to implement the example design using the supported FPGA implementation tools included with the ISE Foundation v7.1i software.

Chapter 7, “Timing Simulation” describes how to perform timing simulation using the supported post-route timing simulation tools, including Cadence NC-Verilog v5.0 and Model Technology ModelSim v5.7b.

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Preface: About This Guide

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource

Description/URL

 

 

Tutorials

Tutorials covering Xilinx design flows, from design entry to

 

verification and debugging

 

http://support.xilinx.com/support/techsup/tutorials/index.htm

 

 

Answer Browser

Database of Xilinx solution records

 

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

 

 

Application Notes

Descriptions of device-specific design techniques and approaches

 

http://support.xilinx.com/apps/appsweb.htm

 

 

Data Sheets

Device-specific information on Xilinx device characteristics,

 

including readback, boundary scan, configuration, length count,

 

and debugging

 

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

 

 

Problem Solvers

Interactive tools that allow you to troubleshoot your design issues

 

http://support.xilinx.com/support/troubleshoot/psolvers.htm

 

 

Tech Tips

Latest news, design tips, and patch information for the Xilinx

 

design environment

 

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

 

 

Conventions

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

Courier font

Messages, prompts, and

speed grade: - 100

program files that the system

 

displays

 

 

 

 

Courier bold

Literal commands you enter in

ngdbuild design_name

a syntactical statement

 

 

 

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Conventions

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Convention

Meaning or Use

Example

 

 

 

 

Variables in a syntax

ngdbuild design_name

 

statement for which you must

 

supply values

 

 

 

 

 

 

See the Development

Italic font

References to other manuals

System Reference Guide

 

for more information.

 

 

 

 

 

 

 

If a wire is drawn so that it

 

Emphasis in text

overlaps the pin of a symbol,

 

the two nets are not

 

 

 

 

connected.

 

 

 

 

An optional entry or

ngdbuild [option_name]

Square brackets [ ]

parameter. However, in bus

 

specifications, such as

design_name

 

bus[7:0], they are required.

 

Braces { }

A list of items from which you

lowpwr ={on|off}

must choose one or more

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

choices

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

.

Repetitive material that has

IOB #2: Name = CLKIN’

.

been omitted

.

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Omitted repetitive material

allow block block_name

 

 

loc1 loc2 ... locn;

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See “Additional Resources”

 

for details.

Blue text

location in the current

See “Title Formats” in Chapter

 

document

 

1 for details.

 

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest speed files.

 

 

 

 

 

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Preface: About This Guide

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Chapter 1

Getting Started

The PCI interface provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions with support for operation at 33 MHz and 66 MHz. This guide defines the supported design flows for both the 32-bit and 64-bit interfaces targeting devices based on the Virtex and Spartan architectures. In addition, an example design is provided in both Verilog-HDL and VHDL that lets you simulate, synthesize, and implement the interface to understand the PCI design flow.

About the Example Design

The example design is a simple user application provided as a training tool and design flow test. The example design consists of the user application Ping, and supporting files for simulation and implementation. The PCI32 interface ships with the ping32 design, and the PCI64 interface ships with the ping64 design. The examples in this document reference ping64. If you are using the 32-bit core, substitute ping32 for ping64.

The Ping design includes a testbench capable of generating simple read and write transactions. This stimulation generation capability is used to set up the configuration space of the design, and then perform some simple transactions. In addition, a special configuration file is provided, and the testbench makes assumptions about the size and number of base address registers used.

Users may change the core options related to implementation, that is, the options that relate to the selected FPGA architecture. However, users must not change core options that alter the functional behavior of the PCI core; such changes cause unpredictable results in the simulation of the example design. For custom designs, users have the flexibility to change the PCI core configuration as described in the PCI v3.0 User Guide.

Step-by-step instructions using supported design tools are provided to simulate, synthesize, and implement the Ping example design.

Additional Documentation

For more information about the PCI interface core, see the following documents, located on the PCI product page:

PCI Release Notes

PCI User Guide

Further information is available in the Mindshare PCI System Architecture text, and the PCI Local Bus Specification, available from the PCI Special Interest Group site.

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Chapter 1: Getting Started

Technical Support

For technical support, visit www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the PCI interface.

Xilinx provides technical support for use of this product as described in the PCI User Guide and the PCI Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the PCI interface core and the documentation supplied with the core.

PCI Interface Core

For comments and suggestions about the PCI interface core, please submit a webcase from www.xilinx.com/support. Be sure to include the following information:

Product name

Core version number

Explanation of your comments

Document

For comments or suggestions about this document, please submit a webcase from www.xilinx.com/support. Be sure to include the following information:

Document title and number

Page number(s) to which your comments refer

Explanation of your comments

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Chapter 2

Installing and Licensing the Core

This chapter provides instructions for installing and obtaining a license for the PCI interface core, which you must do before using it in your designs. The PCI core is provided under the terms of the Xilinx LogiCORE Site License Agreement or the Xilinx LogiCORE Project License Agreement, which conform to the terms of the SignOnce IP License/Project standard defined by the Common License Consortium. Purchase of the PCI core entitles you to technical support and access to updates for a period of one year.

Important note: Please visit the PCI/PCI-X lounge frequently to make sure that you are using the latest version of the core. You can always download the most up-to-date version of the core from the product lounge.

System Requirements

Windows

Windows® 2000 Professional (Service Pack 2-4)

Windows XP Home (Service Pack 1); Windows XP Professional (Service Pack 1)

Solaris/Linux

Sun Solaris™ 8/9

Red Hat® Enterprise Linux 3.0 (32-bit and 64-bit)

Software

ISE 7.1i or higher (Service Pack 4)

Note: If necessary, ISE 7.1i Service Packs can be downloaded from

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=7.1i

Installing the Core

You can install the PCI core in three ways:

Using the CORE Generator IP Updates Installer, which displays a list of compatible updates from which you select the desired core or core update

Performing a manual installation of the appropriate ISE CORE Generator IP Update

Directly downloading it from the PCI lounge, a secured area of the PCI product page

Note: The first two methods apply to configurations of the core delivered through the CORE Generator. To access the CORE Generator full product license or to download the core directly from the PCI lounge, you must purchase the core.

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Chapter 2: Installing and Licensing the Core

CORE Generator IP Updates Installer

1.From the CORE Generator main GUI, choose Tools > Updates Installer to start the Updates Installer.

2.If prompted for a proxy host, contact your administrator to determine the proxy host address and port number you need to get through your firewall.

3.Select 7.1i_IP_Update3 from the list of updates in the Available Packages panel.

4.Click Add To Install Queue to add the update ZIP file to the install queue.

5.Do one of the following:

If prompted to enter a log-in name and password, enter your Xilinx log-in and password.

If you are new to Xilinx, click Create an Account and follow the instructions to create an account. (After creating an account, you will be redirected to the page to download the core.)

6.Click Install All Packages from Queue to download the update.

After downloading the update, the Updates Installer terminates the CORE Generator session and installs the downloaded archive. After the download is complete, you can restart the CORE Generator.

7.To confirm the installation, check the following file:

C:\Xilinx\coregen\install\install_history.

Note: This step assumes your Xilinx software is installed in C:\Xilinx.

Manual Installation: CORE Generator IP Update

1.Close the CORE Generator application if it is running.

2.Download the IP Update ZIP file (Windows) or tar.gz file (UNIX) from the following location and save it to a temporary directory: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=7.1i

If prompted to enter a log-in name and password, enter your Xilinx log-in and password.

If you are new to Xilinx, click Create an Account and follow the instructions to create an account.

3.Do one of the following:

For Windows, unpack the ZIP file using WinZip 7.0 SR-1 or later.

For UNIX, Xilinx recommends that you unpack the tar.gz file using the UNIX command line utilities gunzip and tar. WinZip and GNU tar are not recommended due to differences in the way they handle files with long path names. Please see Xilinx Answer 11162 for details.

4.Extract the ZIP file (ise_71i_ip_update3.zip) or tar.gz (ise_71i_ip_update3.tar.gz) archive to the root directory of your Xilinx software installation. Allow the extractor utility to overwrite all existing files and maintain the directory structure defined in the archive.

5.To verify the root directory of your Xilinx installation, do one of the following:

For Windows: Type echo%XILINX% from a DOS prompt.

For Unix: If you have already installed the Xilinx ISE software, the Xilinx variable defined by your set-up script identifies the location of the Xilinx installation directory. After sourcing the Xilinx set-up script, type echo $XILINX to determine

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the location of the Xilinx installation. Note that you may need system administrator privileges to install the update.

6.Confirm the directory structure in one of the following ways:

For Windows:

<Xilinx_root_directory>\coregen\ip\xilinx\network_ip1_h\com\xilinx \ip\pci64_v30151

For UNIX:

<Xilinx_root_directory>/coregen/ip/xilinx/network_ip1_h/com/xilinx /ip/pci64_v30151

If you do not see this directory structure, recheck the directory to which you extracted the archive and try again.

7.Restart the CORE Generator. During start-up, the CORE Generator automatically detects new versions of IP available in your installation and lets you specify which IP customizers (cores) will be visible in your current CORE Generator project.

8.Choose one of the following options:

Display only the latest versions for all cores in the catalog

Update the catalog view to add only new cores to the display

Make a Custom selection of visible cores in your current project

9.Determine if the installation was successful by verifying that the new cores are visible in the CORE Generator GUI.

10.If the new cores aren’t visible, return to Step 6 to verify the directory structure. If the directory structure is incorrect, return Step 4 to verify that the directory was extracted to the correct location.

For additional assistance installing the IP Update, contact the Xilinx Hotline.

Direct Download of Standalone Core

The PCI core can be downloaded from the Xilinx website and used outside of the CORE Generator by downloading a .zip file containing the core and other necessary supporting files. Note that you must purchase the core to use this option.

1.After purchase, you will receive a letter containing a serial number, which is used to register for access to the lounge, a secured area of the PCI product page. Go to http://www.xilinx.com/products/logicore/lounge/lounge.htm and choose the appropriate link to gain access to the core you purchased.

2.From the core’s product page, click Register to register and request access to the lounge. Xilinx will review your access request and typically grants access to the lounge in 48 hours. (Contact Xilinx Customer Service if you need faster turnaround.)

3.After you receive confirmation of lounge access, click Access Lounge from the appropriate PCI product page and log in.

This page lists the current build of the core as well as previous builds. For new designs or to update an existing design, select the current version of the core.

4.From the table, select the desired version. A page specific to the version appears.

5.Click the link to the .zip file to download it. After saving the .zip file, unzip it to the desired location on your system.

6.If desired, customize the core settings by following the instructions in Chapter 5, “Customizing the PCI Interface” of the PCI v3.0 User Guide.

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Chapter 2: Installing and Licensing the Core

Licensing Options

Evaluation

The method for obtaining an evaluation license is determined by the version of the PCI core you choose.

For the PCI32/33 Virtex™ and Spartan™ core, register on the Xilinx IP Evaluation page at www.xilinx.com/ipcenter/ipevaluation. From this location, access is granted and you can generate your own license.

For the PCI 64/66 core, please contact your locate FAE to request a Full System Hardware Evaluation license key.

Full

The Full license is provided when you purchase the core, and provides full access to all core functionality both in simulation and in hardware, including:

Gate-level functional simulation support

Back annotated gate-level simulation support

Full implementation support including place and route and bitstream generation

Full functionality in the programmed device with no time-outs

Obtaining a Full License

After purchase, a full license for the Xilinx PCI core can be downloaded from the core’s lounge. To create and download a license file for use with the CORE Generator, do the following:

1.After purchase, you will receive a letter containing a serial number, which is used to register for access to the lounge, a secured area of the PCI product page. Go to http://www.xilinx.com/products/logicore/lounge/lounge.htm and choose the appropriate link to gain access to core.

2.From the product page, click Register to register and request access to the lounge. Xilinx will review your access request and typically grants access to the lounge in 48 hours. (Contact Xilinx Customer Service if you need faster turnaround.)

3.After receiving confirmation of lounge access, click Access Lounge from the PCI product page and log in.

4.From the lounge, a link is available at the top of the initial page allowing you to generate a license. Click this link and follow the instructions to fill out the license request form; then click Submit to generate the license. An e-mail containing license and installation instructions will be sent to you immediately.

Direct Download

A CORE Generator license is not required when performing a direct download of PCI-X core, as described in “Direct Download of Standalone Core,” page 15.

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Installing Your License File

After selecting a license option, an email will be sent to you that includes instructions for installing your license file. In addition, information about advanced licensing options and technical support is provided.

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