XICOR X28LC513JI-15, X28LC513J-25, X28LC513J-20, X28LC513J-15, X28LC512TI-25 Datasheet

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X28LC512/X28LC513

512K

X28LC512/X28LC513

64K x 8 Bit

3.3 Volt, Byte Alterable E2PROM

FEATURES

Low VCC Operation: VCC = 3.3V ±10%

Access Time: 150ns

Simple Byte and Page Write —Self-Timed

—No Erase Before Write

—No Complex Programming Algorithms —No Overerase Problem

Low Power CMOS:

—Active: 25mA —Standby: 150 μA

Software Data Protection

—Protects Data Against System Level Inadvertant Writes

High Speed Page Write Capability

Highly Reliable Direct Write™ Cell —Endurance: 10,000 Write Cycles —Data Retention: 100 Years

Early End of Write Detection

DATA Polling

—Toggle Bit Polling

PIN CONFIGURATIONS

PLASTIC DIP

NC

 

1

32

 

VCC

A11

 

 

1

 

 

 

 

 

 

 

A9

 

 

2

 

 

 

 

 

 

 

NC

 

2

31

 

 

WE

 

 

A8

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

A15

 

3

30

 

NC

A13

 

4

 

 

 

 

 

 

A14

 

 

5

A12

 

4

29

 

A14

 

 

 

 

NC

 

 

6

 

 

 

 

A7

 

5

28

 

A13

 

NC

 

7

 

 

 

NC

 

 

8

A6

 

6

27

 

A8

 

 

 

 

 

 

 

 

 

WE

 

 

 

9

 

 

 

 

 

 

 

A5

 

7

26

 

A9

VCC

 

10

 

 

 

 

 

A4

 

8

25

 

A11

 

NC

 

 

11

 

 

 

NC

 

12

 

X28LC512

 

 

 

 

A3

 

9

24

 

 

 

 

 

NC

 

13

 

 

OE

 

 

 

NC

 

 

14

 

 

 

 

 

A2

 

10

23

 

A10

 

 

 

 

 

A15

 

15

 

 

 

 

 

A1

 

11

22

 

 

CE

 

A12

 

 

16

 

 

 

 

 

 

 

 

 

 

 

A0

 

12

21

 

I/O7

 

A7

 

17

 

 

 

 

 

 

 

 

A6

 

18

I/O0

 

13

20

 

 

 

 

 

I/O6

 

A5

 

 

19

 

 

 

 

I/O1

 

14

19

 

I/O5

 

A4

 

20

 

 

 

 

 

 

 

 

I/O2

 

15

18

 

I/04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

16

17

 

I/O3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3005 ILL F02.1

© Xicor, Inc. 1991, 1995, 1996 Patents Pending 3005-3.2 8/5/97 T2/C0/D0 EW

Two PLCC and LCC Pinouts —X28LC512

—X28LC010 E 2PROM Pin Compatible —X28LC513

—Compatible with Lower Density E 2PROMs

DESCRIPTION

The X28LC512/513 is a low-power 64K x 8 E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology. The X28LC512/513 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS.

The X28LC512/513 supports a 128-byte page write operation, effectively providing a 39μs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28LC512/513 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28LC512/513 supports the Software Data Protection option.

 

 

 

 

 

 

PLCC

 

 

 

 

 

 

 

 

12

15

NC

NC

CC

WE

NC

 

 

 

 

 

 

A

A

V

 

 

 

 

 

 

 

 

 

 

 

 

30

 

TSOP

 

 

A7

5 4 3

2

1

32 31 29

A14

 

 

A6

6

 

 

 

 

28

A13

 

 

 

 

 

 

 

 

40

OE

A5

7

 

 

 

 

 

27

A8

 

39

A10

A4

8

X28LC512

 

26

A9

 

38

CE

A3

9

(TOP VIEW)

25

A11

 

37

I/O7

A2

10

 

 

 

 

 

24

OE

 

36

I/O6

A1

11

 

 

 

 

 

23

A10

 

35

I/O5

A0

12

 

 

 

 

 

22

CE

 

34

I/O4

I/O0

13

15 16 17 18 19 20 21

I/O7

 

33

I/O3

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

NC

 

1

2

SS

3

4

5 6

 

 

 

 

 

 

 

 

X28LC512

31

NC

 

I/O

I/O

V

I/O

I/O

I/O

I/O

 

 

 

 

 

 

 

 

3005 ILL F03

 

30

VSS

 

 

 

 

 

 

 

29

NC

 

 

 

PLCC

 

 

 

 

 

28

NC

 

 

12

14

15

CC

 

13

 

 

 

27

I/O2

 

7

WE

 

 

 

26

I/O1

 

A

A A

A V

A

 

 

 

 

 

 

 

 

 

 

30

 

 

25

I/O0

 

 

 

 

 

 

 

 

 

24

A0

A6

5 4 3 2

1

32 31 29

 

A8

 

23

A1

A5

6

 

 

 

 

28

 

A9

 

 

 

 

 

 

 

 

22

A2

A4

7

 

 

 

 

 

27

 

A11

 

21

A3

A3

8

X28LC513

 

26

 

NC

 

 

 

A2

9

(TOP VIEW)

25

 

OE

 

 

 

24

 

 

3005 ILL F22.2

A1

10

 

 

 

 

 

 

A10

 

A0

11

 

 

 

 

 

23

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

NC

12

 

 

 

 

 

22

 

I/O7

 

 

 

I/O0

13

15 16 17 18 19 20

21

I/O6

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

SS

NC

3

4 5

 

 

 

 

 

 

I/O

I/O

V

I/O

I/O

I/O

 

 

3005 ILL F04.1

 

 

 

 

1

Characteristics subject to change without notice

 

 

 

X28LC512/X28LC513

PIN DESCRIPTIONS

Addresses (A –A )

0 15

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers and is used to initiate read operations.

Data In/Data Out (I/O –I/O)

0 7

Data is written to or read from the X28LC512/513 through the I/O pins.

FUNCTIONAL DIAGRAM

Write Enable (WE)

The Write Enable input controls the writing of data to the X28LC512/513.

PIN NAMES

Symbol

Description

 

 

A0–A15

Address Inputs

I/O0–I/O7

Data Input/Output

WE

Write Enable

CE

Chip Enable

 

 

OE

Output Enable

 

 

VCC

3.3V ± 10%

VSS

Ground

NC

No Connect

3005 PGM T01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X BUFFERS

 

512K-BIT

 

 

 

A7–A15

 

 

E2PROM

 

LATCHES AND

 

 

 

 

 

ARRAY

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y BUFFERS

I/O BUFFERS

 

AND LATCHES

A0–A6

LATCHES AND

 

 

DECODER

 

I/O0–I/O7

DATA INPUTS/OUTPUTS

CE

CONTROL

 

OE

LOGIC AND

WE

TIMING

 

VCC

 

VSS

 

3005 ILL F01

2

X28LC512/X28LC513

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28LC512/513 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.

Page Write Operation

The page write feature of the X28LC512/513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28LC512/513 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.

The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100μs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100μs, the internal automatic programming cycle will commence. There is no page write window limitation.

Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100μs.

Write Operation Status Bits

The X28LC512/513 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

I/O

DP

TB

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

RESERVED

TOGGLE BIT

DATA POLLING

3005 ILL F11

DATA Polling (I/O7)

The X28LC512/513 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28LC512/ 513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data.

Toggle Bit (I/O6)

The X28LC512/513 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.

3

XICOR X28LC513JI-15, X28LC513J-25, X28LC513J-20, X28LC513J-15, X28LC512TI-25 Datasheet

X28LC512/X28LC513

DATA Polling I/O7

Figure 2a. DATA Polling Bus Sequence

LAST

WE WRITE

CE

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

VIH

 

HIGH Z

 

 

 

V

OH

I/O7

 

 

 

 

 

 

 

 

VOL

 

 

 

 

 

 

 

 

 

X28LC512

 

 

 

 

 

 

 

READY

A0–A15

An

An

An

An

An

An

An

 

3005 ILL F12

Figure 2b. DATA Polling Software Flow

WRITE DATA

WRITES NO

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

 

ADDRESS

 

IO7

NO

COMPARE?

 

YES

 

X28LC512

 

READY

 

DATA Polling can effectively halve the time for writing to the X28LC512/513. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.

3005 ILL F13

4

X28LC512/X28LC513

The Toggle Bit I/O6

Figure 3a. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

 

 

 

OE

 

 

 

I/O6

*

VOH

HIGH Z

VOL

*

 

 

X28LC512

 

 

 

READY

* Beginning and ending state of I/O6 will vary.

3005 ILL F14

Figure 3b. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

NO

COMPARE

OK?

YES

X28LC512

READY

3005 ILL F15

The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28LC512/513 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for polling the Toggle Bit.

5

X28LC512/X28LC513

HARDWARE DATA PROTECTION

The X28LC512/513 provides three hardware features that protect nonvolatile data from inadvertent writes.

Noise Protection—A WE pulse typically less than 10ns will not initiate a write cycle.

Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently.

SOFTWARE DATA PROTECTION

The X28LC512/513 offers a software controlled data protection feature. The X28LC512/513 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/ -down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable.

The X28LC512/513 can be automatically protected during power-up and power-down without the need for

external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.

Once the software protection is enabled, the X28LC512/ 513 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three-byte enable sequence is not written to the memory array.

SOFTWARE ALGORITHM

Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.

6

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