XICOR X28HC64SM-12, X28HC64SI-90, X28HC64SI-70, X28HC64SI-55, X28HC64SI-12 Datasheet

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X28HC64
1
64K X28HC64 8K x 8 Bit
5 Volt, Byte Alterable E
2
PROM
© Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
3857-3.0 8/5/97 T1/C0/D0 EW
55ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS
—40 mA Active Current Max.
—200 µA Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32µs Typical
Software Data Protection
End of Write Detection
DATA Polling
—Toggle Bit
PIN CONFIGURATIONS
3857 FHD F03
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
4321323130
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
X28HC64
LCC
PLCC
A
7
A
12
NC
NC
V
CC
WE
NC
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
3857 ILL F22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28HC64
A
3
A
4
A
5
A
6
A
7
A
12
NC
NC
V
CC
NC
WE
NC
A
8
A
9
A
11
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
NC
V
SS
NC
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
10
TSOP
3857 FHD F02.1
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/0
4
I/O
3
X28HC64
PLASTIC DIP
FLAT PACK
CERDIP
SOIC
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28HC64 is an 8K x 8 E
2
PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28HC64 is a 5V only device. The
X28HC64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and en-
abling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PGA
X28HC64
11
I/O
0
10
A
0
14
V
SS
9
A
1
8
A
2
7
A
3
6
A
4
5
A
5
2
A
12
28
V
CC
12
I/O
1
13
I/O
2
15
I/O
3
4
A
6
3
A
7
1
NC
16
I/O
4
20
CE
22
OE
24
A
9
17
I/O
5
27
WE
19
I/O
7
21
A
10
23
A
11
25
A
8
18
I/O
6
26
NC
BOTTOM VIEW
3857 FHD F04
2
X28HC64
PIN DESCRIPTIONS
Addresses (A
0
–A
12
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28HC64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
PIN NAMES
Symbol Description
A
0
–A
12
Address Inputs
I/O
0
–I/O
7
Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
+5V
V
SS
Ground
NC No Connect
3857 PGM T01
3857 FHD F01
X BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
65,536-BIT
E
2
PROM
ARRAY
I/O
0
–I/O
7
DATA INPUTS/OUTPUTS
CE
OE
V
CC
V
SS
A
0
–A
12
ADDRESS
INPUTS
WE
FUNCTIONAL DIAGRAM
X28HC64
3
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC64 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
2ms.
Page Write Operation
The page write feature of the X28HC64 allows the entire
memory to be written in 0.25 seconds. Page write allows
two to sixty-four bytes of data to be consecutively written
to the X28HC64 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A
6
through A
12
) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each succes-
sive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling (I/O
7
)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28HC64,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O
6
will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Figure 1. Status Bit Assignment
3857 FHD F11
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
4
X28HC64
DATA Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
3857 FHD F13
WRITE DATA
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
READY
NO
YES
WRITES
COMPLETE?
NO
YES
Figure 3. DATA Polling Software Flow
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
3857 FHD F12
CE
OE
WE
I/O
7
X28HC64
READY
LAST
WRITE
HIGH Z
V
OL
V
IH
A
0
–A
12
An An An An An An
V
OH
An
X28HC64
5
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC64 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
3857 FHD F15
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
READY
COMPARE
OK?
NO
YES
LAST WRITE
3857 FHD F14
CE
OE
WE
I/O
6
X28HC64
READY
V
OH
V
OL
LAST
WRITE
HIGH Z
* Beginning and ending state of I/O
6
will vary.
*
*
6
X28HC64
HARDWARE DATA PROTECTION
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
Default V
CC
Sense—All write functions are inhibited
when V
CC
is 3V typically.
Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data protec-
tion feature. The X28HC64 is shipped from Xicor with
the software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once V
CC
was stable.
The X28HC64 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28HC64
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data. Once the page load cycle has been completed, the
device will automatically be returned to the data pro-
tected state.
X28HC64
7
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
3857 FHD F16
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically dis-
able further writes unless another command is issued to
deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3857 FHD F17
CE
WE
(V
CC
)
WRITE
PROTECTED
V
CC
0V
DATA
ADDR
AA
1555
55
0AAA
A0
1555
t
BLC MAX
WRITES
OK
BYTE
OR
PAGE
t
WC
WRITE LAST
BYTE TO
LAST ADDRESS
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
AFTER t
WC
RE-ENTERS DATA
PROTECTED STATE
WRITE DATA AA
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
OPTIONAL BYTE
OR PAGE WRITE
ALLOWED
8
X28HC64
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
Figure 9. Software Sequence to
Deactivate Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E
2
PROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After t
WC
,
the X28HC64 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3857 ILL F18.2
CE
WE
STANDARD
OPERATING
MODE
Vcc
DATA
ADDR
AA
1555
55
0AAA
80
1555
t
WC
AA
1555
55
0AAA
20
1555
WRITE DATA 55
TO ADDRESS
0AAA
3857 ILL F19.2
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 20
TO ADDRESS
1555
WRITE DATA AA
TO ADDRESS
1555
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