X28HC256
256K |
X28HC256 |
32K x 8 Bit |
5 Volt, Byte Alterable E2PROM
FEATURES
•Access Time: 70ns
•Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V PP Control Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
•Low Power CMOS:
—Active: 60mA
—Standby: 500 μA
•Software Data Protection
—Protects Data Against System Level Inadvertent Writes
•High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
•Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
A14 |
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1 |
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28 |
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VCC |
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A12 |
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A7 |
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3 |
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A13 |
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A6 |
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A8 |
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A5 |
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A9 |
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A4 |
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23 |
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A11 |
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A3 |
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OE |
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X28HC256 |
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A2 |
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A10 |
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A1 |
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CE |
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A0 |
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I/O7 |
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I/O0 |
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I/O6 |
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I/O1 |
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I/O5 |
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I/O2 |
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I/04 |
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VSS |
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I/O3 |
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3859 FHD F02
LCC
PLCC
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14 |
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CC |
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WE |
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A |
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32 |
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30 |
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A6 |
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A8 |
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A5 |
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28 |
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A9 |
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A4 |
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27 |
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A11 |
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A3 |
8 |
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X28HC256 |
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26 |
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NC |
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9 |
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A2 |
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OE |
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A1 |
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A10 |
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A0 |
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23 |
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CE |
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NC |
12 |
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I/O7 |
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I/O0 |
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I/O6 |
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SS |
NC |
3 |
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I/O |
I/O |
V |
I/O |
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I/O |
I/O |
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3859 FHD F03
DESCRIPTION
The X28HC256 is a second generation high performance CMOS 32K x 8 E2PROM. It is fabricated with Xicor’s proprietary, textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile memory.
The X28HC256 supports a 128-byte page write operation, effectively providing a 24μs/byte write cycle and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum 100,000 write cycles per byte and an inherent data retention of 100 years.
TSOP
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A2 |
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1 |
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A3 |
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A1 |
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A4 |
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A0 |
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30 |
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A5 |
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I/O0 |
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A6 |
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I/O1 |
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A7 |
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I/O2 |
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A12 |
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A14 |
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VSS |
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8 |
X28HC256 |
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NC |
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9 |
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VCC |
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I/O3 |
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NC |
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I/O4 |
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WE |
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I/O5 |
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21 |
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A13 |
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I/O6 |
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20 |
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A8 |
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I/O7 |
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14 |
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A9 |
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CE |
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15 |
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18 |
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A11 |
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A10 |
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16 |
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17 |
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OE |
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3859 ILL F22
©Xicor, Inc. 1991, 1995 Patents Pending |
1 |
Characteristics subject to change without notice |
3859-2.8 8/5/97 T1/C0/D0 EW |
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X28HC256
PIN DESCRIPTIONS
Addresses (A –A )
0 14
The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (I/O –I/O)
0 7
Data is written to or read from the X28HC256 through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the X28HC256.
FUNCTIONAL DIAGRAM
PIN NAMES
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A0–A14 |
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Address Inputs |
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I/O0–I/O7 |
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Data Input/Output |
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WE |
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Write Enable |
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CE |
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Chip Enable |
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OE |
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Output Enable |
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VCC |
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+5V |
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VSS |
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Ground |
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NC |
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No Connect |
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3859 PGM T01 |
PIN CONFIGURATION |
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PGA |
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I/O1 |
I/O2 |
I/O3 |
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I/O5 |
I/O6 |
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12 |
13 |
15 |
17 |
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18 |
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I/O0 |
A0 |
VSS |
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I/O4 |
I/O7 |
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11 |
10 |
14 |
16 |
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19 |
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A1 |
A2 |
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A10 |
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CE |
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9 |
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20 |
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21 |
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A3 |
A4 |
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A11 |
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OE |
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7 |
6 |
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22 |
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23 |
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A5 |
A12 |
VCC |
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A9 |
A8 |
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5 |
2 |
28 |
24 |
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25 |
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A6 |
A7 |
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A13 |
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A14 |
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WE |
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4 |
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1 |
27 |
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26 |
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X28HC256 |
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3859 FHD F04 |
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(BOTTOM VIEW) |
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X BUFFERS |
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256K-BIT |
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E2PROM |
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LATCHES AND |
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ARRAY |
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DECODER |
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A0–A14
ADDRESS
INPUTS
I/O BUFFERS
Y BUFFERS AND LATCHES
LATCHES AND
DECODER
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I/O0–I/O7 |
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DATA INPUTS/OUTPUTS |
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CE |
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CONTROL |
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OE |
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LOGIC AND |
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TIMING |
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VCC |
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VSS |
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3859 FHD F01 |
3859 FHD F01 |
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2
X28HC256
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100μs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100μs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100μs.
Write Operation Status Bits
The X28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O |
DP |
TB |
5 |
4 |
3 |
2 |
1 |
0 |
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RESERVED
TOGGLE BIT
DATA POLLING
3859 FHD F11
DATA Polling (I/O7)
The X28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC256, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read and write operations.
3
X28HC256
DATA POLLING I/O7
Figure 2. DATA Polling Bus Sequence
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WE |
WRITE |
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CE |
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OE |
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VIH |
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HIGH Z |
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VOH |
I/O7 |
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VOL |
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X28HC256 |
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READY |
A0–A14 |
An |
An |
An |
An |
An |
An |
An |
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3859 FHD F12 |
Figure 3. DATA Polling Software Flow
WRITE DATA
WRITES NO
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST |
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ADDRESS |
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IO7 |
NO |
COMPARE? |
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YES |
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X28HC256 |
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READY |
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DATA Polling can effectively halve the time for writing to the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.
3859 FHD F13
4
X28HC256
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE |
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OE |
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I/O6 |
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VOH |
HIGH Z |
VOL |
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X28HC256 |
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READY |
* I/O6 beginning and ending state of I/O6 will vary.
3859 FHD F14
Figure 5. Toggle Bit Software Flow
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28HC256
READY
3859 FHD F15
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.
5
X28HC256
HARDWARE DATA PROTECTION
The X28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes.
•Default VCC Sense—All write functions are inhibited when VCC is ≤ 3.5V Typically.
•Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC256 offers a software controlled data protection feature. The X28HC256 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable.
The X28HC256 can be automatically protected during power-up and power-down without the need for external
circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
6
X28HC256
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
VCC |
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0V |
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DATA |
AA |
55 |
A0 |
tWC |
WRITE |
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ADDRESS |
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5555 |
2AAA |
5555 |
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WRITES |
PROTECTED |
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CE |
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OK |
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≤tBLC MAX |
BYTE |
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OR |
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WE |
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3859 FHD F16
Figure 7. Write Sequence for
Software Data Protection
WRITE DATA AA TO ADDRESS 5555
WRITE DATA 55 TO ADDRESS 2AAA
WRITE DATA A0
TO ADDRESS 5555
BYTE/PAGE LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS OPTIONAL
BYTE OR
PAGE WRITE
WRITE LAST ALLOWED
BYTE TO
LAST ADDRESS
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28HC256 will be write protected during power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not be interrupted.
3859 FHD F06
7
X28HC256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
VCC |
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DATA |
AA |
55 |
80 |
AA |
55 |
20 |
tWC |
STANDARD |
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ADDRESS |
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5555 |
2AAA |
5555 |
5555 |
2AAA |
5555 |
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OPERATING |
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MODE |
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CE |
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WE
3859 FHD F18
Figure 9. Write Sequence for resetting Software Data Protection
WRITE DATA AA TO ADDRESS 5555
WRITE DATA 55 TO ADDRESS 2AAA
WRITE DATA 80 TO ADDRESS 5555
WRITE DATA AA TO ADDRESS 5555
WRITE DATA 55 TO ADDRESS 2AAA
WRITE DATA 20 TO ADDRESS 5555
AFTER tWC,
RE-ENTERS
UNPROTECTED
STATE
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC256 will be in standard operating mode.
Note: Once initiated, the sequence of write operations should not be interrupted.
3859 FHD F19
8