X28C64
64K |
X28C64 |
8K x 8 Bit |
5 Volt, Byte Alterable E2PROM
FEATURES
•150ns Access Time
•Simple Byte and Page Write —Single 5V Supply
—No External High Voltages or V PP Control Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms —No Overerase Problem
•Low Power CMOS
—60mA Active Current Max. —200 μA Standby Current Max.
•Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 0.625 sec. Typical —Effective Byte Write Cycle Time: 78 μs Typical
•Software Data Protection
•End of Write Detection
— DATA Polling
—Toggle Bit
•High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years
•JEDEC Approved Byte-Wide Pinout
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
NC |
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1 |
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28 |
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VCC |
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A12 |
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2 |
27 |
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WE |
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A7 |
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3 |
26 |
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NC |
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A6 |
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4 |
25 |
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A8 |
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A5 |
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5 |
24 |
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A9 |
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A4 |
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6 |
23 |
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A11 |
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A3 |
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7 |
22 |
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OE |
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X28C64 |
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A2 |
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8 |
21 |
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A10 |
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A1 |
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9 |
20 |
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CE |
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A0 |
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10 |
19 |
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I/O7 |
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I/O0 |
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11 |
18 |
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I/O6 |
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I/O1 |
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12 |
17 |
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I/O5 |
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I/O2 |
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13 |
16 |
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I/04 |
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VSS |
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14 |
15 |
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I/O3 |
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3853 FHD F02
LCC
PLCC
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7 |
12 |
NC |
NC |
CC |
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WE |
NC |
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A |
A |
V |
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4 |
3 |
2 |
1 |
32 |
31 |
30 |
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A6 |
5 |
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29 |
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A8 |
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A5 |
6 |
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28 |
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A9 |
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A4 |
7 |
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27 |
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A11 |
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A3 |
8 |
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X28C64 |
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26 |
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NC |
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9 |
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25 |
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A2 |
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OE |
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A1 |
10 |
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24 |
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A10 |
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A0 |
11 |
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23 |
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CE |
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NC |
12 |
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22 |
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I/O7 |
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I/O0 |
13 |
15 |
16 |
17 |
18 |
19 |
21 |
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I/O6 |
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14 |
20 |
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1 |
2 |
SS |
NC |
3 |
4 |
5 |
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I/O |
I/O |
V |
I/O |
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I/O |
I/O |
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3853 FHD F03
DESCRIPTION
The X28C64 is an 8K x 8 E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C64 is a 5V only device. The X28C64 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs.
The X28C64 supports a 64-byte page write operation, effectively providing a 78μs/byte write cycle and enabling the entire memory to be typically written in 0.625 seconds. The X28C64 also features DATA and Toggle Bit Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C64 includes a user-optional software data protection mode that further enhances Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
TSOP
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A2 |
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1 |
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32 |
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A3 |
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A1 |
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2 |
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31 |
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A4 |
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A0 |
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3 |
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30 |
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A5 |
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I/O0 |
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4 |
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29 |
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A6 |
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I/O1 |
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5 |
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28 |
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A7 |
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I/O2 |
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6 |
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27 |
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A12 |
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NC |
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7 |
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26 |
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NC |
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VSS |
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8 |
X28C64 |
25 |
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NC |
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NC |
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9 |
24 |
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VCC |
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I/O3 |
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10 |
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23 |
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NC |
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I/O4 |
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11 |
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22 |
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WE |
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I/O5 |
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12 |
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21 |
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NC |
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I/O6 |
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13 |
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20 |
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A8 |
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I/O7 |
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14 |
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19 |
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A9 |
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CE |
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15 |
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18 |
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A11 |
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A10 |
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16 |
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17 |
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OE |
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3853 ILL F23.1
© Xicor, Inc. 1991, 1995 Patents Pending |
1 |
Characteristics subject to change without notice |
3853-2.7 4/2/96 T0/C3/D2 NS |
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X28C64
PIN DESCRIPTIONS
Addresses (A –A )
0 12
The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read operations.
PIN NAMES
Symbol |
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Description |
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A0–A12 |
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Address Inputs |
I/O0–I/O7 |
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Data Input/Output |
WE |
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Write Enable |
CE |
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Chip Enable |
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OE |
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Output Enable |
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VCC |
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+5V |
VSS |
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Ground |
NC |
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No Connect |
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3853 PGM T01 |
FUNCTIONAL DIAGRAM |
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Data In/Data Out (I/O –I/O)
0 7
Data is written to or read from the X28C64 through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the X28C64.
PIN CONFIGURATION
PGA
I/O1 |
I/O2 |
I/O3 |
I/O5 |
I/O6 |
12 |
13 |
15 |
17 |
18 |
I/O0 |
A0 |
VSS |
I/O4 |
I/O7 |
11 |
10 |
14 |
16 |
19 |
A1 |
A2 |
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CE |
A10 |
9 |
8 |
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20 |
21 |
A3 |
A4 |
X28C64 |
OE |
A11 |
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7 |
6 |
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22 |
23 |
A5 |
A12 |
VCC |
A9 |
A8 |
5 |
2 |
28 |
24 |
25 |
A6 |
A7 |
NC |
WE |
NC |
4 |
3 |
1 |
27 |
26 |
BOTTOM VIEW
3853 FHD F04
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65,536-BIT |
X BUFFERS |
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E2PROM |
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LATCHES AND |
ARRAY |
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DECODER |
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A0–A12
ADDRESS
INPUTS
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Y BUFFERS |
I/O BUFFERS |
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AND LATCHES |
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LATCHES AND |
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DECODER |
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I/O0–I/O7 |
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DATA INPUTS/OUTPUTS |
CE |
CONTROL |
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OE |
LOGIC AND |
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WE |
TIMING |
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VCC |
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VSS |
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3853 FHD F01 |
2
X28C64
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C64 allows the entire memory to be written in 0.625 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28C64 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A12) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100μs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100μs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100μs.
Write Operation Status Bits
The X28C64 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O |
DP |
TB |
5 |
4 |
3 |
2 |
1 |
0 |
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RESERVED
TOGGLE BIT
DATA POLLING
3853 FHD F11
DATA Polling (I/O7)
The X28C64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C64, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the X28C64 is in the protected state and an illegal write operation is attempted DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
3
X28C64
DATA Polling I/O7
Figure 2. DATA Polling Bus Sequence
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LAST |
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WE |
WRITE |
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CE |
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OE |
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VIH |
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HIGH Z |
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V |
OH |
I/O7 |
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VOL |
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X28C64 |
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READY |
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A0–A12 |
An |
An |
An |
An |
An |
An |
An |
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3853 FHD F12 |
Figure 3. DATA Polling Software Flow
WRITE DATA
WRITES NO
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST |
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ADDRESS |
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IO7 |
NO |
COMPARE? |
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YES |
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X28C64 |
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READY |
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3853 FHD F13 |
DATA Polling can effectively halve the time for writing to the X28C64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.
4
X28C64
The Toggle Bit I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE |
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OE |
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I/O6 |
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VOH |
HIGH Z |
* |
VOL |
* |
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X28C64 |
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READY |
* Beginning and ending state of I/O6 will vary.
3853 FHD F14
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28C64
READY
3853 FHD F15
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C64 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.
5
X28C64
HARDWARE DATA PROTECTION
The X28C64 provides three hardware features (compatible with X2864A) that protect nonvolatile data from inadvertent writes.
•Noise Protection—A WE pulse typically less than 20ns will not initiate a write cycle.
•Default VCC Sense—All write functions are inhibited when VCC is ≤3V typically.
•Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28C64 offers a software controlled data protection feature. The X28C64 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable.
The X28C64 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C64 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window enabling the host to write from one to sixty-four bytes of data*. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
Note: *Once the three-byte sequence is issued it must be followed by a valid byte or page write operation.
6
X28C64
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
VCC |
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(VCC) |
0V |
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DATA |
AA |
55 |
A0 |
tWPH2 |
tWC |
WRITE |
ADDRESS |
1555 |
0AAA |
1555 |
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WRITES |
PROTECTED |
CE |
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OK |
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≤tBLC MAX |
BYTE |
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WE |
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OR |
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PAGE |
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3853 FHD F16
Figure 7. Write Sequence for Software Data Protection
WRITE DATA AA TO ADDRESS
1555
WRITE DATA 55 TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
3853 FHD F17
3853 FHD F17
Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C64 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C64 will be write protected during power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not be interrupted.
7
X28C64
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
VCC |
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DATA |
AA |
55 |
80 |
AA |
55 |
20 |
³tWC |
STANDARD |
OPERATING |
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ADDRESS |
1555 |
0AAA |
1555 |
1555 |
0AAA |
1555 |
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MODE |
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CE |
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WE
3853 FHD F18.1
Figure 9. Software Sequence to Deactivate Software Data Protection
WRITE DATA AA TO ADDRESS
1555
WRITE DATA 55 TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS 1555
WRITE DATA AA TO ADDRESS 1555
WRITE DATA 55 TO ADDRESS
0AAA
WRITE DATA 20 TO ADDRESS 1555
3853 ILL F19.2
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C64 will be in standard operating mode.
Note: Once initiated, the sequence of write operations should not be interrupted.
8