XICOR X28C513JMB-15, X28C513JMB-12, X28C513JM-90, X28C513JM-25, X28C513JM-20 Datasheet

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XICOR X28C513JMB-15, X28C513JMB-12, X28C513JM-90, X28C513JM-25, X28C513JM-20 Datasheet

X28C512/X28C513

512K

X28C512/X28C513

64K x 8 Bit

5 Volt, Byte Alterable E2PROM

FEATURES

Access Time: 90ns

Simple Byte and Page Write —Single 5V Supply

No External High Voltages or V PP Control Circuits

—Self-Timed

—No Erase Before Write

—No Complex Programming Algorithms —No Overerase Problem

Low Power CMOS:

—Active: 50mA —Standby: 500 μA

Software Data Protection

—Protects Data Against System Level Inadvertant Writes

High Speed Page Write Capability

Highly Reliable Direct Write™ Cell —Endurance: 100,000 Write Cycles —Data Retention: 100 Years

Early End of Write Detection

DATA Polling

—Toggle Bit Polling

Two PLCC and LCC Pinouts —X28C512

—X28C010 E 2PROM Pin Compatible —X28C513

—Compatible with Lower Density E 2PROMs

DESCRIPTION

The X28C512/513 is an 64K x 8 E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C512/513 is a 5V only device. The X28C512/513 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS.

The X28C512/513 supports a 128-byte page write operation, effectively providing a 39μs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512/513 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512/513 supports the Software Data Protection option.

PIN CONFIGURATIONS

 

 

 

 

TSOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A11

1

 

 

 

 

 

 

 

 

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

A9

2

 

 

 

 

 

 

 

 

39

A10

 

 

 

 

 

 

 

 

 

 

 

A8

3

 

 

 

 

 

 

 

 

38

CE

 

 

 

 

PLASTIC DIP

 

 

 

 

 

 

A13

4

 

 

 

 

 

 

 

 

37

I/O7

 

 

 

 

 

 

 

 

 

A14

5

 

 

 

 

 

 

 

 

36

I/O6

 

 

 

 

CERDIP

 

 

 

 

 

 

NC

6

 

 

 

 

 

 

 

 

35

I/O5

 

 

 

FLAT PACK

 

 

 

 

 

 

NC

7

 

 

 

 

 

 

 

 

34

I/O4

 

 

 

 

SOIC (R)

 

 

 

 

 

 

NC

8

 

 

 

 

 

 

 

 

33

I/O3

 

 

 

 

 

 

 

 

 

 

 

WE

9

 

 

 

 

 

 

 

 

32

NC

 

 

 

 

 

 

 

 

 

 

 

VCC

10

 

 

X28C512

 

 

 

 

31

NC

NC

 

1

32

 

VCC

NC

11

 

 

 

 

 

 

 

 

30

VSS

 

 

 

 

 

 

 

 

 

 

 

NC

12

 

 

 

 

 

 

 

 

29

NC

NC

 

2

31

 

 

WE

 

NC

13

 

 

 

 

 

 

 

 

28

NC

A15

 

3

30

 

NC

NC

14

 

 

 

 

 

 

 

 

27

I/O2

 

 

A15

15

 

 

 

 

 

 

 

 

26

I/O1

 

 

 

 

 

 

 

 

 

A12

 

4

29

 

A14

A12

16

 

 

 

 

 

 

 

 

25

I/O0

 

 

A7

17

 

 

 

 

 

 

 

 

24

A0

A7

 

5

28

 

A13

A6

18

 

 

 

 

 

 

 

 

23

A1

 

 

 

 

 

 

 

 

 

 

 

A5

19

 

 

 

 

 

 

 

 

22

A2

A

6

 

6

27

 

A

8

 

 

A4

20

 

 

 

 

 

 

 

 

21

A3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

 

7

26

 

A9

 

 

 

 

 

PGA

 

 

 

 

 

 

 

3856 ILL F22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

8

25

 

A11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X28C512

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

9

24

 

 

OE

 

 

 

 

I/O0

I/O2

I/O3

I/O5

I/O6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

10

23

 

A10

 

 

 

15

17

19

21

 

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

A0

I/O1

VSS

I/O4

I/O7

CE

 

 

 

 

A1

 

11

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

13

14

16

18

20

 

23

24

 

 

 

 

 

 

 

 

 

 

 

 

 

A

0

 

12

21

 

I/O

 

 

A2

A3

 

 

 

 

 

A10

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

12

11

 

 

 

 

 

25

26

 

 

 

 

 

 

I/O0

 

13

20

 

I/O6

 

 

A4

A5

BOTTOM

 

 

 

A11

A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O1

 

14

19

 

I/O5

 

10

9

 

VIEW

 

 

 

27

28

 

 

 

 

 

 

I/O

2

 

15

18

 

I/0

4

 

 

A6

A7

 

 

 

 

 

A8

A13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

7

 

 

 

 

 

29

30

 

 

 

 

 

 

VSS

 

16

17

 

I/O3

 

 

A12

A15

NC

VCC

NC

NC

A14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

5

2

36

34

 

32

31

 

 

 

 

 

 

 

 

 

 

 

3856 FHD F01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

NC

NC

 

WE

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

3

1

35

 

33

 

 

 

 

 

 

 

 

3856 FHD F02

PLCC / LCC

 

12

15

NC

NC

CC

WE

NC

 

 

 

A

A

V

 

 

 

 

 

 

 

 

 

30

 

A7

5 4 3

2

1

32 31 29

 

A14

A6

6

 

 

 

 

28

 

A13

 

 

 

 

 

 

A5

7

 

 

 

 

 

27

 

A8

A4

8

 

X28C512

 

26

 

A9

A3

9

 

 

25

 

A11

(TOP VIEW)

 

A2

10

 

 

 

 

 

24

 

OE

A1

11

 

 

 

 

 

23

 

A10

A0

12

 

 

 

 

 

22

 

CE

I/O0

13

15 16 17 18 19 20

21

I/O7

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

SS

3

4

5 6

 

 

 

I/O

I/O

V

I/O

I/O

I/O

I/O

 

 

 

 

 

 

 

 

 

 

3856 FHD F03

 

7

12

14

15

CC

WE

13

 

 

 

A

A A

A V

A

 

 

 

 

 

 

 

 

 

30

 

A6

5 4 3 2

1

32 31 29

 

A8

A5

6

 

 

 

 

28

 

A9

 

 

 

 

 

 

A4

7

 

 

 

 

 

27

 

A11

A3

8

 

X28C513

 

26

 

NC

A2

9

 

 

25

 

OE

(TOP VIEW)

 

24

 

A1

10

 

 

 

 

 

 

A10

A0

11

 

 

 

 

 

23

 

CE

NC

12

 

 

 

 

 

22

 

I/O7

I/O0

13

15 16 17 18 19 20

21

I/O6

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

SS

NC

3

4 5

 

 

 

I/O

I/O

V

I/O

I/O

I/O

 

 

3856 FHD F04

© Xicor, Inc. 1991, 1995, 1996 Patents Pending

1

Characteristics subject to change without notice

3856-3.2 8/5/97 T1/C0/D0 EW

 

 

 

X28C512/X28C513

PIN DESCRIPTIONS

Addresses (A –A )

0 15

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers and is used to initiate read operations.

Data In/Data Out (I/O –I/O)

0 7

Data is written to or read from the X28C512/513 through the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the X28C512/513.

FUNCTIONAL DIAGRAM

PIN NAMES

Symbol

Description

 

 

A0–A15

Address Inputs

I/O0–I/O7

Data Input/Output

WE

Write Enable

 

 

CE

Chip Enable

 

 

OE

Output Enable

VCC

+5V

VSS

Ground

NC

No Connect

3856 PGM T01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X BUFFERS

 

512K-BIT

A7–A15

 

 

E2PROM

 

LATCHES AND

 

 

 

 

 

ARRAY

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y BUFFERS

I/O BUFFERS

 

AND LATCHES

A0–A6

LATCHES AND

 

 

DECODER

 

 

 

I/O0–I/O7

 

 

DATA INPUTS/OUTPUTS

CE

CONTROL

 

 

 

OE

LOGIC AND

 

WE

TIMING

 

 

 

VCC

 

 

VSS

 

3856 FHD F05

2

X28C512/X28C513

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C512/513 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.

Page Write Operation

The page write feature of the X28C512/513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28C512/513 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.

The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100μs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100μs, the internal automatic programming cycle will commence. There is no page write window limitation.

Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100μs.

Write Operation Status Bits

The X28C512/513 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

I/O

DP

TB

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

RESERVED

TOGGLE BIT

DATA POLLING

3856 FHD F06

DATA Polling (I/O7)

The X28C512/513 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C512/ 513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data.

Toggle Bit (I/O6)

The X28C512/513 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.

3

X28C512/X28C513

DATA Polling I/O7

Figure 2a. DATA Polling Bus Sequence

LAST

WE WRITE

CE

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

VIH

 

HIGH Z

 

 

 

V

OH

I/O7

 

 

 

 

 

 

 

 

VOL

 

 

 

 

 

 

 

 

 

X28C512/513

 

 

 

 

 

 

 

READY

A0–A15

An

An

An

An

An

An

An

 

3856 FHD F07.1

Figure 2b. DATA Polling Software Flow

WRITE DATA

WRITES NO

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

 

ADDRESS

 

IO7

NO

COMPARE?

 

YES

 

X28C512

 

READY

 

 

3856 FHD F08

DATA Polling can effectively halve the time for writing to the X28C512/513. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.

4

X28C512/X28C513

The Toggle Bit I/O6

Figure 3a. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

 

 

 

OE

 

 

 

I/O6

*

VOH

HIGH Z

VOL

*

 

 

X28C512/513

 

 

 

READY

 

 

 

3856 FHD F09.1

* Beginning and ending state of I/O6 will vary.

Figure 3b. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

NO

COMPARE

OK?

YES

X28C512

READY

3856 FHD F10

The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C512/513 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for polling the Toggle Bit.

5

X28C512/X28C513

HARDWARE DATA PROTECTION

The X28C512/513 provides three hardware features that protect nonvolatile data from inadvertent writes.

Noise Protection—A WE pulse typically less than 10ns will not initiate a write cycle.

Default VCC Sense—All write functions are inhibited when VCC is 3.6V.

Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently.

SOFTWARE DATA PROTECTION

The X28C512/513 offers a software controlled data protection feature. The X28C512/513 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/ -down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable.

The X28C512/513 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.

Once the software protection is enabled, the X28C512/ 513 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three-byte enable sequence is not written to the memory array.

SOFTWARE ALGORITHM

Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.

6

X28C512/X28C513

Software Data Protection

Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write

VCC

 

 

 

 

 

(VCC)

0V

 

 

 

 

 

 

DATA

AA

55

A0

WRITES

tWC

WRITE

ADDR

5555

2AAA

5555

OK

 

 

 

 

 

PROTECTED

CE

 

 

 

 

 

 

 

 

 

tBLC MAX

BYTE

 

 

WE

 

 

 

OR

 

 

 

 

 

PAGE

 

 

NOTE: All other timings and control pins are per page write timing requirements.

3856 FHD F11

Figure 4b. Write Sequence for Software Data Protection

WRITE DATA AA TO ADDRESS 5555

WRITE DATA 55 TO ADDRESS 2AAA

WRITE DATA A0 TO ADDRESS 5555

WRITE DATA XX

TO ANY

ADDRESS

OPTIONAL

BYTE/PAGE

LOAD OPERATION

WRITE LAST

BYTE TO

LAST ADDRESS

AFTER tWC

RE-ENTERS DATA

PROTECTED STATE

3856 FHD F12

Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28C512/513 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C512/513 will be write protected during power-down and after any subsequent power-up. The state of A15 while executing the algorithm is don’t care.

Note: Once initiated, the sequence of write operations should not be interrupted.

7

X28C512/X28C513

Resetting Software Data Protection

Figure 5a. Reset Software Data Protection Timing Sequence

VCC

 

 

 

 

 

 

 

 

 

 

 

STANDARD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

³tWC

 

 

DATA

AA

55

80

AA

55

20

 

 

 

 

 

 

OPERATING

 

 

 

ADDR

5555

2AAA

5555

5555

2AAA

5555

 

 

 

 

MODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

WE

NOTE: All other timings and control pins are per page write timing requirements.

3856 FHD F13

Figure 5b. Software Sequence to Deactivate Software Data Protection

WRITE DATA AA TO ADDRESS 5555

WRITE DATA 55 TO ADDRESS 2AAA

WRITE DATA 80 TO ADDRESS 5555

WRITE DATA AA TO ADDRESS 5555

WRITE DATA 55 TO ADDRESS 2AAA

WRITE DATA 20 TO ADDRESS 5555

3856 FHD F14

In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C512/513 will be in standard operating mode.

Note: Once initiated, the sequence of write operations should not be interrupted.

8

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