XICOR X28C256TMB-35, X28C256TMB-25, X28C256TMB-20, X28C256TMB, X28C256TM-35 Datasheet

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X28C256

256K

X28C256

32K x 8 Bit

5 Volt, Byte Alterable E2PROM

FEATURES

Access Time: 200ns

Simple Byte and Page Write

— Single 5V Supply

—No External High Voltages or V PP Control Circuits

Self-Timed

No Erase Before Write

No Complex Programming Algorithms —No Overerase Problem

Low Power CMOS:

—Active: 60mA —Standby: 200 μA

Software Data Protection

Protects Data Against System Level Inadvertent Writes

High Speed Page Write Capability

Highly Reliable Direct WriteCell

Endurance: 100,000 Write Cycles

Data Retention: 100 Years

Early End of Write Detection

DATA Polling

—Toggle Bit Polling

DESCRIPTION

The X28C256 is an 32K x 8 E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C256 is a 5V only device. The X28C256 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs.

The X28C256 supports a 64-byte page write operation, effectively providing a 78μs/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28C256 also features DATA and Toggle Bit Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C256 includes a user-optional software data protection mode that further enhances Xicor’s hardware write protect capability.

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

PIN CONFIGURATION

PLASTIC DIP

CERDIP

FLAT PACK

SOIC

A14

 

1

 

 

28

 

VCC

 

 

 

A12

 

2

27

 

 

WE

 

 

A7

 

3

26

 

A13

 

A6

 

4

25

 

A8

 

A5

 

5

24

 

A9

 

A4

 

6

23

 

A11

 

A3

 

7

22

 

 

OE

 

 

 

 

X28C256

 

 

 

 

 

 

A2

 

8

21

 

A10

 

A1

 

9

20

 

 

CE

 

 

A0

 

10

19

 

I/O7

 

I/O0

 

11

18

 

I/O6

 

 

I/O1

 

12

17

 

I/O5

 

 

I/O2

 

13

16

 

I/04

 

VSS

 

14

15

 

I/O3

 

3855 FHD F02

LCC

PLCC

 

7

12

14

NC

CC

 

WE

13

 

 

 

 

 

 

 

 

 

A

A

A

V

 

A

 

 

 

 

4

3

2

1

32

31

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

5

 

 

 

 

 

 

29

 

A8

A5

6

 

 

 

 

 

 

28

 

A9

A4

7

 

 

 

 

 

 

27

 

A11

A3

8

 

X28C256

 

 

26

 

NC

 

9

 

 

 

25

 

 

 

A2

 

 

 

 

OE

 

 

 

 

 

 

 

A1

10

 

 

 

 

 

 

24

 

A10

A0

11

 

 

 

 

 

 

23

 

CE

 

NC

12

 

 

 

 

 

 

22

 

I/O7

I/O0

13

15

16

17

18

19

21

 

I/O6

 

14

20

 

 

 

 

1

2

SS

NC

3

4

5

 

 

 

 

I/O

I/O

V

I/O

 

I/O

I/O

 

 

 

3855 FHD F03

A2 1 A1 2 A0 3 I/O0 4

I/O1 5 I/O2 6 NC 7

VSS 8 NC 9

I/O3 10 I/O4 11 I/O5 12 I/O6 13 I/O7 14

CE 15 A10 16

TSOP

32 A3

31 A4

30 A5

29 A6

28 A7

27 A12

26 A14

X28C256 25 NC 24 VCC

23 NC

22 WE

21 A13 20 A8 19 A9 18 A11

17 OE

3855 ILL F23

© Xicor, Inc. 1991, 1995 Patents Pending

1

Characteristics subject to change without notice

3855-1.9 8/1/97 T1/C0/D8 EW

 

 

 

X28C256

PIN DESCRIPTIONS

Addresses (A –A )

0 14

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers and is used to initiate read operations.

Data In/Data Out (I/O –I/O)

0 7

Data is written to or read from the X28C256 through the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the X28C256.

FUNCTIONAL DIAGRAM

PIN NAMES

Symbol

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

A0–A14

 

 

 

Address Inputs

I/O0–I/O7

 

 

 

Data Input/Output

WE

 

 

 

Write Enable

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

Chip Enable

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

Output Enable

VCC

 

 

 

+5V

 

 

VSS

 

 

 

Ground

NC

 

 

 

No Connect

 

 

 

 

 

 

 

 

 

 

3855 PGM T01

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O1

I/O2

I/O3

I/O5

I/O6

 

 

12

13

 

15

17

 

 

18

 

 

I/O0

A0

VSS

I/O4

I/O7

 

 

11

10

 

14

16

 

 

19

 

 

A1

A2

 

 

 

 

 

A10

 

 

 

 

CE

 

 

 

 

9

8

 

 

20

 

 

21

 

 

 

 

 

X28C256

 

 

 

 

 

 

 

A3

A4

 

 

OE

A11

 

 

7

6

 

 

22

 

 

23

 

 

A5

A12

VCC

 

A9

A8

 

 

5

2

 

28

24

 

 

25

 

 

A6

A7

A14

 

 

A13

 

 

 

WE

 

 

 

4

3

 

1

27

 

 

26

3855 FHD F04

 

 

 

 

 

 

 

 

 

 

 

 

BOTTOM VIEW

 

 

 

 

 

 

 

 

 

 

 

 

 

X BUFFERS

 

256K-BIT

E2PROM

LATCHES AND

ARRAY

DECODER

 

A0–A14

ADDRESS

INPUTS

I/O BUFFERS

Y BUFFERS AND LATCHES

LATCHES AND

DECODER

I/O0–I/O7

DATA INPUTS/OUTPUTS

CE

CONTROL

 

OE

LOGIC AND

WE

TIMING

 

VCC

 

VSS

 

3855 FHD F01

2

X28C256

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.

Page Write Operation

The page write feature of the X28C256 allows the entire memory to be written in 2.5 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28C256 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.

The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100μs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100μs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100μs.

Write Operation Status Bits

The X28C256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

I/O

DP

TB

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

RESERVED

TOGGLE BIT

DATA POLLING

3855 FHD F11

DATA Polling (I/O7)

The X28C256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C256, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the X28C256 is in the protected state and an illegal write operation is attempted DATA Polling will not operate.

Toggle Bit (I/O6)

The X28C256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.

3

XICOR X28C256TMB-35, X28C256TMB-25, X28C256TMB-20, X28C256TMB, X28C256TM-35 Datasheet

X28C256

DATA POLLING I/O7

Figure 2. DATA Polling Bus Sequence

 

LAST

 

 

 

 

 

 

WE

WRITE

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

VIH

 

HIGH Z

 

 

 

VOH

I/O7

 

 

VOL

 

 

 

 

 

 

 

 

X28C256

 

 

 

 

 

 

 

READY

A0–A14

An

An

An

An

An

An

An

 

 

 

 

 

 

 

3855 FHD F12

Figure 3. DATA Polling Software Flow

WRITE DATA

WRITES NO

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

 

ADDRESS

 

IO7

NO

COMPARE?

 

YES

 

X28C256

 

READY

 

DATA Polling can effectively halve the time for writing to the X28C256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.

3855 FHD F13

4

X28C256

THE TOGGLE BIT I/O6

Figure 4. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

 

 

 

OE

 

 

 

I/O6

*

VOH

HIGH Z

VOL

*

 

 

X28C256

 

 

 

READY

* Beginning and ending state of I/O6 will vary.

3855 FHD F14

Figure 5. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

NO

COMPARE

OK?

YES

X28C256

READY

3855 FHD F15

The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.

5

X28C256

HARDWARE DATA PROTECTION

The X28C256 provides three hardware features (compatible with X28C64) that protect nonvolatile data from inadvertent writes.

Noise Protection—A WE pulse typically less than 20ns will not initiate a write cycle.

Default VCC Sense—All write functions are inhibited when VCC is 3.5V typically.

Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity.

SOFTWARE DATA PROTECTION

The X28C256 offers a software controlled data protection feature. The X28C256 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable.

The X28C256 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.

Once the software protection is enabled, the X28C256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device.

Software Algorithm

Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window enabling the host to write from one to sixty-four bytes of data.* Once the page load cycle has been completed, the device will automatically be returned to the data protected state.

*Note: Once the three-byte sequence is issued it must be followed by a valid byte or page write operation.

6

X28C256

SOFTWARE DATA PROTECTION

Figure 6. Timing Sequence—Byte or Page Write

VCC

 

 

 

 

 

(VCC)

0V

 

 

 

 

 

 

DATA

AA

55

A0

tWPH2

tWC

WRITE

ADDR.

5555

2AAA

5555

 

 

 

 

 

WRITES

PROTECTED

CE

 

 

 

 

OK

 

 

 

 

tBLC MAX

BYTE

 

WE

 

 

 

 

OR

 

 

 

 

 

PAGE

 

3855 FHD F16

Figure 7. Write Sequence for

Software Data Protection

WRITE DATA AA TO ADDRESS 5555

WRITE DATA 55 TO ADDRESS 2AAA

WRITE DATA A0

TO ADDRESS 5555

BYTE/PAGE LOAD ENABLED

WRITE DATA XX

TO ANY

ADDRESS

WRITE LAST

BYTE TO

LAST ADDRESS

AFTER tWC

RE-ENTERS DATA

PROTECTED STATE

Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C256 will be write protected during power-down and after any subsequent power-up.

Note: Once initiated, the sequence of write operations should not be interrupted.

3855 FHD F17

7

X28C256

RESETTING SOFTWARE DATA PROTECTION

Figure 8. Reset Software Data Protection Timing Sequence

VCC

DATA AA

55

80

AA

55

20

 

³tWC

 

 

 

STANDARD

 

 

 

 

OPERATING

 

 

ADDR. 5555

2AAA

5555

5555

2AAA

5555

 

 

 

 

 

MODE

 

 

 

 

 

 

 

 

 

 

 

CE

WE

3855 FHD F18

Figure 9. Software Sequence to

Deactivate Software Data Protection

WRITE DATA AA TO ADDRESS 5555

WRITE DATA 55 TO ADDRESS 2AAA

WRITE DATA 80 TO ADDRESS 5555

WRITE DATA AA TO ADDRESS 5555

WRITE DATA 55 TO ADDRESS 2AAA

WRITE DATA 20 TO ADDRESS 5555

3855 FHD F19

In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C256 will be in standard operating mode.

Note: Once initiated, the sequence of write operations should not be interrupted.

8

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