XICOR X2816CSI-90, X2816CSI-20, X2816CSI-15, X2816CSI-12, X2816CS-90 Datasheet

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XICOR X2816CSI-90, X2816CSI-20, X2816CSI-15, X2816CSI-12, X2816CS-90 Datasheet

X2816C

16K

X2816C

2048 x 8 Bit

5 Volt, Byte Alterable E2PROM

FEATURES

90ns Access Time

Simple Byte and Page Write —Single 5V Supply

—No External High Voltages or V PP Control Circuits

—Self-Timed

—No Erase Before Write

—No Complex Programming Algorithms —No Overerase Problem

High Performance Advanced NMOS Technology

Fast Write Cycle Times

—16 Byte Page Write Operation

—Byte or Page Write Cycle: 5ms Typical

—Complete Memory Rewrite: 640ms Typical

—Effective Byte Write Cycle Time: 300 μs

Typical

DATA Polling

—Allows User to Minimize Write Cycle Time

JEDEC Approved Byte-Wide Pinout

High Reliability —Endurance: 10,000 Cycles —Data Retention: 100 Years

PIN CONFIGURATION

PLASTIC DIP

SOIC

A7

1

24

VCC

A6

2

23

A8

A5

3

22

A9

A4

4

21

 

WE

 

A3

5

20

 

 

OE

 

 

A2

6

19

A10

 

 

X2816C

 

 

 

 

 

A1

7

18

 

CE

 

 

 

A0

8

17

I/O7

I/O0

9

16

I/O6

I/O1

10

15

I/O5

I/O2

11

14

I/04

VSS

12

13

I/O3

3852 FHD F02.1

DESCRIPTION

The Xicor X2816C is a 2K x 8 E2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor Programmable nonvolatile memories it is a 5V only device. The X2816C features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs and EPROMs.

The X2816C supports a 16-byte page write operation, typically providing a 300μs/byte write cycle, enabling the entire memory to be written in less than 640ms. The X2816C also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle.

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

LCC

 

 

 

PLCC

 

 

 

 

 

 

 

7

NC

NC

NC

CC

 

WE

NC

 

 

 

 

 

 

 

 

 

A

V

 

 

 

 

 

4

3

2

1

32

31

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

5

 

 

 

 

 

 

29

 

A8

A5

6

 

 

 

 

 

 

28

 

A9

A4

7

 

 

 

 

 

 

27

 

NC

A3

8

 

X2816C

 

 

26

 

NC

 

9

 

 

 

25

 

 

 

A2

 

 

 

 

OE

 

 

 

 

 

 

 

A1

10

 

 

 

 

 

 

24

 

A10

A0

11

 

 

 

 

 

 

23

 

CE

 

NC

12

 

 

 

 

 

 

22

 

I/O7

I/O0

13

15

16

17

18

19

21

 

I/O6

 

14

20

 

 

 

 

1

2

SS

NC

3

4

5

 

 

 

 

I/O

I/O

V

I/O

 

I/O

I/O

 

3852 FHD F03

 

 

 

 

 

 

 

 

 

 

©Xicor, 1995 Patents Pending

Characteristics subject to change without notice

3852-1.4 3/27/96 T2/C3/D5 NS

1

X2816C

PIN DESCRIPTIONS

Addresses (A –A )

0 10

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers and is used to initiate read operations.

FUNCTIONAL DIAGRAM

PIN NAMES

Symbol

Description

 

 

A0–A10

Address Inputs

I/O0–I/O7

Data Input/Output

WE

Write Enable

 

 

CE

Chip Enable

OE

Output Enable

 

 

VCC

+5V

VSS

Ground

NC

No Connect

 

 

3852 PGM T01

X BUFFERS

 

16,384-BIT

LATCHES AND

 

E2PROM

 

DECODER

 

ARRAY

A0–A10

ADDRESS

INPUTS

I/O BUFFERS

Y BUFFERS AND LATCHES

LATCHES AND

DECODER

I/O0–I/O7

DATA INPUTS/OUTPUTS

CE

OE

CONTROL

LOGIC

WE

VCC

VSS

3852 FHD F01

 

2

X2816C

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW and WE HIGH. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2816C supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.

Page Write Operation

The page write feature of the X2816C allows the entire memory to be typically written in 640ms. Page write allows two to sixteen bytes of data to be consecutively written to the X2816C prior to the commencement of the internal programming cycle. Although the host system may read data from any other device in the system to transfer to the X2816C, the destination page address of the X2816C should be the same on each subsequent strobe of the WE and CE inputs. That is, A4 through A10 must be the same for each transfer of data to the X2816C during a page write cycle.

The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive

byte load cycle, started by the WE HIGH to LOW transition, must begin within 20μs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 20μs, the internal automatic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 20μs.

DATA Polling

The X2816C features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2816C, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data.

WRITE PROTECTION

There are three features that protect the nonvolatile data from inadvertent writes.

Noise Protection—A WE pulse which is typically less than 10ns will not initiate a write cycle.

VCC Sense—All functions are inhibited when VCC is 3V, typically.

Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH during power-up and power-down, will inhibit inadvertent writes. Write cycle timing specifications must be observed concurrently.

ENDURANCE

Xicor E2PROMs are designed and tested for applications requiring extended endurance.

3

X2816C

SYSTEM CONSIDERATIONS

Because the X2816C is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus.

To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.

Because the X2816C has two power modes, standby and active, proper decoupling of the memory array is of

prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1μF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger.

In addition, it is recommended that a 4.7μF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.

4

X2816C

ABSOLUTE MAXIMUM RATINGS*

 

Temperature under Bias

–10°C to +85°C

X2816C .......................................

X2816CI .....................................

–65°C to +135°C

Storage Temperature .......................

–65°C to +150°C

Voltage on any Pin with

 

Respect to VSS ..................................

–1V to +7V

D.C. Output Current .............................................

5mA

Lead Temperature (Soldering, 10 seconds)...... 300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

 

 

 

Commercial

0°C

+70°C

Industrial

–40°C

+85°C

 

 

 

3852 PGM T02.2

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage

Limits

 

 

X2816C

5V ±10%

 

 

3852 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

 

 

 

Limits

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min.

Typ.(1)

 

Max.

Units

Test Conditions

ICC

VCC Current (Active)

 

70

 

110

mA

CE = OE = VIL

 

 

 

 

 

 

 

All I/O’s = Open

 

 

 

 

 

 

 

Other Inputs = VCC

ISB1

VCC Current (Standby)

 

35

 

50

mA

CE = VIH, OE = VIL

 

 

 

 

 

 

 

All I/O’s = Open

 

 

 

 

 

 

 

Other Inputs = VCC

ILI

Input Leakage Current

 

 

 

10

μA

VIN = VSS to VCC

ILO

Output Leakage Current

 

 

 

10

μA

VOUT = VSS to VCC, CE = VIH

VlL(2)

Input LOW Voltage

–1

 

 

0.8

V

 

VIH(2)

Input HIGH Voltage

2

 

 

VCC +1

V

 

VOL

Output LOW Voltage

 

 

 

0.4

V

IOL = 2.1mA

VOH

Output HIGH Voltage

2.4

 

 

 

V

IOH = –400μA

3852 PGM T02.2

Notes: (1) Typical values are for TA = 25°C and nominal supply voltage and are not tested.

(2) VIL min. and VIH max. are for reference only and are not tested.

5

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