XICOR X25041P-3, X25041P-2,7, X25041P, X25041SM-3, X25041SM-2,7 Datasheet

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X25041

4K

X25041

512 x 8 Bit

SPI Serial E2PROM with Block LockTM Protection

FEATURES

1MHz Clock Rate

SPI Modes (0,1 & 1,0)

512 X 8 Bits

—4 Byte Page Mode

Low Power CMOS

—150 μA Standby Current

—3mA Active Current

2.7V To 5.5V Power Supply

Block Lock Protection

—Protect 1/4, 1/2 or all of E 2PROM Array

Built-in Inadvertent Write Protection —Power-Up/Power-Down protection circuitry —Write Latch

—Write Protect Pin

Self-Timed Write Cycle

—5ms Write Cycle Time (Typical)

High Reliability

—Endurance: 100,000 cycles per byte —Data Retention: 100 Years

—ESD protection: 2000V on all pins

8-Lead PDlP Package

8-Lead SOIC Package

DESCRIPTION

The X25041 is a CMOS 4096-bit serial E2PROM, internally organized as 512 x 8. The X25041 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus.

The X25041 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25041 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25041 disabling all write attempts, thus providing a mechanism for limiting end user capability of altering the memory.

The X25041 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years.

FUNCTIONAL DIAGRAM

 

STATUS

WRITE

 

 

 

PROTECT

X DECODE

512 BYTE

 

REGISTER

 

LOGIC

LOGIC

ARRAY

 

 

 

 

 

32

32 X 32

 

 

 

 

SO

 

 

 

 

SI

COMMAND

 

 

 

DECODE

 

 

 

SCK

 

32

 

AND

 

32 X 32

 

 

CS

CONTROL

 

 

 

HOLD

LOGIC

 

 

 

 

 

 

 

 

 

 

64

64 X 32

 

 

 

 

 

WRITE

 

 

 

 

CONTROL

 

 

 

 

AND

 

 

 

WP

TIMING

 

 

 

LOGIC

 

 

 

 

 

4

8

 

 

 

 

 

 

 

Y DECODE

 

 

 

 

DATA REGISTER

Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.

 

 

6556 FHD F01

 

 

 

 

 

 

 

 

 

©Xicor, Inc. 1995, 1996 Patents Pending

1

Characteristics subject to change without notice

6556-1.2 6/10/96 T6/C1/D0 NS

 

 

X25041

PIN DESCRIPTIONS

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the rising edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the falling edge of the serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the falling edge of the clock input, while data on the SO pin change after the rising edge of the clock input.

Chip Select (CS)

When CS is HIGH, the X25041 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25041 will be in the standby power mode. CS LOW enables the X25041, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation.

Write Protect (WP)

When WP is LOW, nonvolatile writes to the X25041 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25041. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is HIGH. To resume communication, HOLD is brought HIGH, again while SCK is HIGH. If the pause feature is not used, HOLD should be held HIGH at all times.

PIN CONFIGURATION

 

 

 

 

 

 

 

DIP/SOIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

8

 

 

 

 

 

 

CS

 

 

 

 

 

VCC

 

 

 

 

SO

 

2

7

 

 

HOLD

 

 

 

 

 

 

 

X25041

 

 

 

 

WP

 

3

6

 

 

SCK

VSS

 

4

5

 

 

SI

 

 

 

 

 

 

 

 

 

 

 

6556 FHD F02

 

 

 

 

 

 

 

 

 

 

 

 

PIN NAMES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

CS

 

 

Chip Select Input

SO

 

 

Serial Output

SI

 

 

Serial Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCK

 

 

Serial Clock Input

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

 

Write Protect Input

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

Ground

 

 

VCC

 

 

Supply Voltage

HOLD

 

 

Hold Input

 

 

6556 PGM T01

2

X25041

PRINCIPLES OF OPERATION

The X25041 is a 512 x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families.

The X25041 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the falling SCK. CS must be LOW during the entire operation.

Table 1 contains a list of the instructions and their codes. All instructions, addresses and data are transferred MSB first.

Data input is sampled on the first falling edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock

line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the

X25041 into a “PAUSE” condition. After releasing HOLD, the X25041 will resume operation from the point when HOLD was first asserted.

Write Enable Latch

The X25041 contains a “write enable” latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle.

Table 1. Instruction Set

Status Register

The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

X

X

X

X

BP1

BP0

WEL

WIP

 

 

 

 

 

 

 

 

6556 PGM T02

BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations.

The Write-In-Process (WIP) bit indicates whether the X25041 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”.

The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When set to a “1”, the latch is set, when set to a “0”, the latch is reset.

The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25041 is divided into four 1024-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below.

Status Register Bits

Array Addresses

 

 

 

BP1

BP0

Protected

 

 

 

0

0

None

 

 

 

0

1

$180–$1FF

 

 

 

1

0

$100–$1FF

 

 

 

1

1

$000–$1FF

6556 PGM T03

Instruction Name

Instruction Format*

Operation

 

 

 

 

WREN

0000

0110

Set the Write Enable Latch (Enable Write Operations)

 

 

 

 

WRDI

0000

0100

Reset the Write Enable Latch (Disable Write Operations)

 

 

 

RDSR

0000 0101

Read Status Register

 

 

 

WRSR

0000 0001

Write Status Register

 

 

 

 

READ

0000

A8011

Read Data from Memory Array beginning at selected address

WRITE

0000

A8010

Write Data to Memory Array beginning at Selected Address

 

 

 

(1 to 32 Bytes)

 

 

 

6556 PGM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

3

X25041

Clock and Data Timing

Data input on the SI line is latched on the falling edge of SCK. Data is output on the SO line by the rising edge of SCK.

Read Sequence

When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25041, followed by the 8-bit address. Bit 3 of the Read Data instruction contains address A8. This bit is used to select the upper or lower half of the address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($1FF) the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure 1.

To read the status register, the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the read status register opcode is sent, the contents of the status register are shifted out on the SO line. Figure 2 illustrates the read status register sequence.

Write Sequence

Prior to any attempt to write data into the X25041, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25041. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored.

To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a twenty-four clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 4 bytes of data to the X25041. The only restriction is the 4 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written.

For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid.

To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5, 6 and 7 must be “0”. Figure 6 illustrates this sequence.

While the write is in progress following a status register or E2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH.

Hold Operation

The HOLD input should be HIGH (at VIH) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be

resumed. The only restriction is the SCK input must be HIGH when HOLD is first pulled LOW and SCK must

also be HIGH when HOLD is released.

The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor.

4

XICOR X25041P-3, X25041P-2,7, X25041P, X25041SM-3, X25041SM-2,7 Datasheet

X25041

Operational Notes

The X25041 powers-up in the following state:

The device is in the low power standby state.

A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.

SO pin is high impedance.

The “write enable” latch is reset.

Figure 1. Read E2PROM Array Operation Sequence

Data Protection

The following circuitry has been included to prevent inadvertent writes:

The “write enable” latch is reset upon power-up.

A WREN instruction must be issued to set the “write enable” latch.

CS must come HIGH at the proper clock count in order to start a write cycle.

CS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

 

SCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INSTRUCTION

 

 

 

 

 

BYTE ADDRESS

 

 

 

 

 

 

 

 

 

 

SI

 

 

 

8

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

9TH BIT OF ADDRESS

 

 

 

 

 

 

 

 

DATA OUT

 

 

 

HIGH IMPEDANCE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

SO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6556 FHD F14.1

Figure 2. Read Status Register Operation Sequence

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SCK

INSTRUCTION

SI

DATA OUT

HIGH IMPEDANCE

SO 7 6 5 4 3 2 1 0

MSB

6556 ILL F13

5

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