XICOR X24F064VI-5, X24F064VI, X24F064VE-5, X24F032PE, X24F032P-5 Datasheet

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APPLICATION NOTE

A V A I L A B L E

AN76 • AN78 • AN81 • AN87

64K/32K/16K

X24F064/032/016

 

8K/4K/2K x 8 Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SerialFlashTM Memory with Block LockTM Protection

 

 

FEATURES

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

1.8V to 3.6V or 5V “Univolt” Read and

The X24F064/032/016 is a CMOS SerialFlash

 

 

Program Power Supply Versions

 

 

 

Memory Family, internally organized 8K/4K/2K x 8.

 

 

Low Power CMOS

 

 

 

The family features a serial interface and software

 

 

—Active Read Current Less Than 1mA

protocol allowing operation on a simple two wire bus.

 

 

—Active Program Current Less Than 3mA

Device select inputs (S0, S1, S2) allow up to eight

 

 

—Standby Current Less Than 1 A

 

 

 

 

 

Internally Organized 8K/4K/2K x 8

 

 

 

devices to share a common two wire bus.

 

 

New Programmable Block Lock Protection

A Program Protect Register accessed at the highest

 

 

—Software Write Protection

 

 

 

address location, provides three new programming

 

 

—Programmable hardware Write Protect

protection features: Software Programming Protection,

 

 

Block Lock (0, 1/4, 1/2, or all of the Flash

Block Lock Protection, and Hardware Programming

 

 

Memory array)

 

 

 

Protection. The Software Programming Protection

 

 

2 Wire Serial Interface

 

 

 

feature prevents any nonvolatile writes to the device

 

 

Bidirectional Data Transfer Protocol

until the WEL bit in the program protect register is set.

 

 

32 Byte Sector Programming

 

 

 

The Block LockTM Protection feature allows the user to

 

 

Self Timed Program Cycle

 

 

 

individually protect four blocks of the array by program-

 

 

—Typical Programming Time of 5ms

ming two bits in the programming protect register. The

 

 

Per Sector

 

 

 

Programmable Hardware Program Protect feature

 

 

High Reliability

 

 

 

allows the user to install each device with PP tied to

 

 

—Endurance: 100,000 cycles per byte

VCC, program the entire memory array in place, and

 

 

—Data Retention: 100 Years

 

 

 

then enable the hardware programming protection by

 

 

Available Packages

 

 

 

programming a PPEN bit in the program protect

 

 

—8-Lead PDIP

 

 

 

register. After this, selected blocks of the array,

 

 

—8-Lead SOIC (JEDEC)

 

 

 

including the program protect register itself, are

 

 

—14-Lead TSSOP (X24F032/016)

 

 

 

permanently protected from being programmed.

 

 

—20-Lead TSSOP (X24F064)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTIONAL DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA REGISTER

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SECTOR DECODE LOGIC

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COMMAND

 

 

 

DECODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DECODE

 

 

 

 

 

 

 

 

SECTORED

 

 

 

S0/S0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AND CONTROL

 

 

 

 

 

 

 

 

 

 

 

MEMORY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

ARRAY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S1/S

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2/S

2

 

 

 

 

 

 

 

 

 

 

 

PROGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROTECT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PP

 

 

 

 

 

PROGRAMMING

 

 

HIGH VOLTAGE

 

 

 

 

 

 

 

 

CONTROL LOGIC

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SerialFlash Memory and Block Lock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6686 ILL F01.5

Protection are trademarks of Xicor, Inc.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Xicor, 1995, 1996 Patents Pending

1

 

 

 

 

 

 

 

 

 

Characteristics subject to change without notice

 

 

6686-3.8 8/29/96 T3/C0/D0 SH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X24F064/032/016

Xicor SerialFlash Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the pullup resistor selection graph at the end of this data sheet.

Device Select (S0, S0, S1, S1, S2, S2)

The device select inputs are used to set the device select bits of the 8-bit slave address. This allows multiple devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS).

Program Protect (PP)

The program protect input controls the hardware program protect feature. When held LOW, hardware program protection is disabled and the X24F064/ 032/016 can be programmed normally. When this input is held HIGH, and the PPEN bit in the program protect register is set HIGH, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the program protect register itself.

PIN NAMES

 

 

Symbol

Description

 

 

 

 

 

 

 

 

S0,

 

0, S1,

 

1, S2,

 

2

Device Select Inputs

S

S

S

 

 

SDA

Serial Data

 

 

 

 

 

 

SCL

Serial Clock

 

 

 

 

 

 

PP

Program Protect

 

 

 

 

 

 

VSS

Ground

 

 

VCC

Supply Voltage

 

 

NC

No Connect

 

 

 

 

 

 

 

 

6686 FRM T01.1

PIN CONFIGURATION

X24F016

8-LEAD DIP & SOIC

 

S0

 

1

8

 

VCC

 

 

 

 

 

 

S

1

 

2

7

 

PP

 

 

 

S2

 

3

6

 

SCL

 

 

 

 

VSS

 

4

5

 

SDA

 

 

X24F032

8-LEAD DIP & SOIC

 

 

 

 

 

 

 

 

 

 

S0

 

1

8

 

VCC

 

 

 

S1

 

2

7

 

PP

 

 

 

S

2

 

3

6

 

SCL

 

 

VSS

 

4

5

 

SDA

 

 

 

 

X24F064

 

 

 

8-LEAD DIP & SOIC

 

NC

 

 

 

 

 

1

8

 

VCC

 

 

 

 

 

S1

 

2

7

 

PP

 

 

 

S

2

 

3

6

 

SCL

 

 

VSS

 

4

5

 

SDA

 

 

 

 

 

 

 

 

 

 

14-LEAD TSSOP

 

 

 

S0

 

1

14

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

S1

 

 

2

 

PP

 

 

 

 

NC

 

 

3

12

 

NC

NC

 

4

11

 

NC

 

 

NC

 

5

10

 

NC

 

 

 

S2

 

 

6

9

 

SCL

 

 

 

 

 

 

 

 

 

7

8

 

SDA

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14-LEAD TSSOP

 

 

 

S

0

 

1

14

 

VCC

 

 

 

S1

 

2

13

 

PP

 

 

NC

 

3

12

 

NC

NC

 

4

11

 

NC

 

NC

 

5

10

 

NC

 

 

 

 

 

 

6

9

 

SCL

 

S

2

 

 

 

7

8

 

SDA

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20-LEAD TSSOP

 

 

NC

 

 

 

 

 

NC

 

 

1

20

 

 

 

 

NC

 

 

 

2

19

 

VCC

 

 

 

 

 

 

 

 

 

 

 

S1

 

 

 

3

18

 

PP

 

 

 

 

 

 

NC

 

 

4

17

 

NC

NC

 

 

 

5

16

 

NC

 

 

 

 

NC

 

 

 

 

 

6

15

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

S2

 

 

 

 

 

14

 

SCL

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

8

13

 

SDA

 

 

 

 

9

 

NC

 

 

 

 

 

 

12

 

NC

 

 

 

 

10

11

 

NC

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6686 ILL F02.4

2

XICOR X24F064VI-5, X24F064VI, X24F064VE-5, X24F032PE, X24F032P-5 Datasheet

X24F064/032/016

DEVICE OPERATION

The X24F064/032/016 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24F064/032/016 will be considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24F064/032/016 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

SCL

SDA

DATA STABLE DATA CHANGE

6686 ILL F04

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (2.7V)

(6)tPR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal program operation.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

6686 ILL F05

3

X24F064/032/016

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

The X24F064/032/016 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24F064/032/016 will respond with an acknowledge after the receipt of each subsequent eight-bit word.

In the read mode the X24F064/032/016 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24F064/032/016 will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the X24F064/032/016 to the standby power mode and place the device into a known state.

SCL FROM

 

 

 

MASTER

1

8

9

DATA OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

6686 ILL F06

4

X24F064/032/016

DEVICE ADDRESSING

Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next two bits are the device select bits. A system could have up to eight X24F032/016’s on the bus or up to four 24F064’s on the bus. The device addresses are defined by the state of the S0, S1, and S2 inputs. Note some of the slave addresses must be the inverse of the corresponding input pin.

Figure 4. Slave Address

 

 

 

 

 

X24F064

 

 

 

 

 

DEVICE

 

 

 

HIGH ORDER

 

 

 

 

SELECT

 

 

SECTOR ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2

 

S1

A12

 

A11

 

A10

 

 

 

 

 

 

 

 

A9

A8

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X24F032

 

 

 

 

 

 

 

DEVICE

 

 

 

 

HIGH ORDER

 

 

 

 

 

SELECT

 

 

 

SECTOR ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2

 

S1

S0

 

A11

 

A10

 

 

 

 

 

 

 

 

 

A9

A8

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEVICE

 

 

 

X24F016

 

 

 

 

 

 

 

TYPE

 

DEVICE

 

 

 

 

HIGH ORDER

 

 

 

IDENTIFIER

 

SELECT

 

 

 

SECTOR ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

S2

S1

 

S0

 

A10

 

 

 

 

 

 

 

 

 

 

 

A9

A8

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6686 ILL F07.4

Figure 5. Sector Programming

Also included in the slave address is an extension of the array’s address which is concatenated with the eight bits of address in the sector address field, providing direct access to the entire SerialFlash Memory array.

The last bit of the slave address defines the operation to be performed. When set HIGH a read operation is selected, when set LOW a program operation is selected.

Following the start condition, the X24F064/032/016 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct comparison of the device select inputs, the X24F064/032/016 outputs an acknowledge on the SDA line. Depending on the state

of the R/W bit, the X24F064/032/016 will execute a read or program operation.

PROGRAMMING OPERATIONS

The X24F064/032/016 offers a 32-byte sector programming operation. For a program operation, the X24F064/032/016 requires a second address field. This field contains the address of the first byte in the sector. Upon receipt of the address, comprised of eight bits, the X24F064/032/016 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then transmits 31 more bytes. After the receipt of each byte, the X24F064/032/016 will respond with an acknowledge.

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

SLAVE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

BUS ACTIVITY:

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

ADDRESS SECTOR ADDRESS

 

 

DATA n

 

 

DATA n+1

 

DATA n+31

 

MASTER

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

SDA LINE

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS ACTIVITY:

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

X24F016/032/064

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

6686 ILL F10.3

5

X24F064/032/016

Flow 1. ACK Polling Sequence

PROGRAM OPERATION

 

COMPLETED

 

 

ENTER ACK POLLING

 

ISSUE

 

 

START

 

 

ISSUE SLAVE

 

ISSUE STOP

ADDRESS AND R/W = 0

 

ACK

NO

 

RETURNED?

 

 

YES

 

 

NEXT

NO

 

OPERATION

 

 

 

A WRITE?

 

 

YES

 

 

ISSUE SECTOR

 

ISSUE STOP

ADDRESS

 

PROCEED

 

PROCEED

 

 

6686 ILL F09.1

After the receipt of each byte, the five low order address bits are internally incremented by one. The high order bits of the sector address remain constant. If the master should transmit more or less than 32 bytes prior to generating the stop condition, the contents of the sector cannot be guaranteed. All inputs are disabled until completion of the internal program cycle. Refer to Figure 5 for the address, acknowledge and data transfer sequence.

Acknowledge Polling

The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Flow 1.

READ OPERATIONS

Read operations are initiated in the same manner as

program operations with the exception that the R/W bit of the slave address is set HIGH. There are three basic read operations: current address read, random read and sequential read.

It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.

6

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