XICOR X24C16S8MB-3,5, X24C16S8MB-3, X24C16S8MB-2,7, X24C16S8M-3,5, X24C16S8MB Datasheet

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XICOR X24C16S8MB-3,5, X24C16S8MB-3, X24C16S8MB-2,7, X24C16S8M-3,5, X24C16S8MB Datasheet

PreliminaryX24C16 Information

16K

X24C16

2048 x 8 Bit

Serial E2PROM

FEATURES

2.7V to 5.5V Power Supply

Low Power CMOS

—Active Read Current Less Than 1 mA —Active Write Current Less Than 3 mA

—Standby Current Less Than 50 μA

Internally Organized 2048 x 8

2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

Sixteen Byte Page Write Mode —Minimizes Total Write Time Per Byte

Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years

8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC Packages

DESCRIPTION

The X24C16 is a CMOS 16,384 bit serial E2PROM, internally organized 2048 X 8. The X24C16 features a serial interface and software protocol allowing operation on a simple two wire bus.

The X24C16 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology.

The X24C16 utilizes Xicor’s proprietary Direct WriteTM cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

FUNCTIONAL DIAGRAM

 

 

 

 

 

(8) VCC

 

 

 

 

 

 

(4) VSS

 

 

 

 

 

 

(7) TEST

 

 

 

START CYCLE

 

H.V. GENERATION

 

 

 

 

 

 

 

 

 

 

TIMING

 

 

 

 

 

 

(5) SDA

START

 

 

 

 

& CONTROL

 

 

 

 

 

 

STOP

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

LOGIC

 

 

 

 

SLAVE ADDRESS

 

 

 

 

E2PROM

 

REGISTER

 

 

XDEC

 

(6) SCL

LOAD

INC

 

128 X 128

+COMPARATOR

 

 

(3) A2

 

WORD

 

 

 

(2) A1

 

ADDRESS

 

 

 

 

COUNTER

 

 

 

(1) A0

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

YDEC

 

 

 

 

 

 

8

 

 

 

PIN

 

CK

DOUT

 

 

 

 

 

 

 

 

 

 

DATA REGISTER

 

DOUT

 

 

 

 

 

 

ACK

 

 

 

 

 

3840 FHD F01

© Xicor, 1991 Patents Pending

1

Characteristics subject to change without notice

 

 

3840-1.1 7/29/96 T1/C0/D0 SH

X24C16

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet.

Address (A0, A1, A2)

The A0, A1 and A2 inputs are unused by the X24C16, however, they must be tied to VSS to insure proper device operation.

PIN NAMES

Symbol

Description

 

 

A0–A2

Address Inputs

SDA

Serial Data

 

 

SCL

Serial Clock

TEST

Hold at VSS

VSS

Ground

VCC

Supply Voltage

NC

No Connect

 

 

3840 PGM T01

PIN CONFIGURATION

 

 

 

DIP/SOIC

 

 

 

 

 

 

A0

 

1

8

VCC

 

 

A1

 

2

7

TEST

 

 

 

 

X24C16

 

A2

 

3

6

SCL

 

VSS

 

4

5

SDA

 

3840 FHD F02

SOIC

NC

 

 

 

 

1

14

 

 

 

 

NC

 

 

 

 

 

 

 

A0

 

 

 

 

2

13

 

 

 

 

VCC

 

 

 

 

 

 

 

 

A1

 

 

 

 

3

12

 

 

 

 

TEST

 

 

 

 

 

 

 

 

NC

 

 

 

 

4

X24C16 11

 

 

 

 

NC

A2

 

 

 

 

5

10

 

 

 

 

SCL

 

 

 

 

 

 

 

 

VSS

 

 

 

 

6

9

 

 

 

 

SDA

 

 

 

 

 

 

 

 

NC

 

 

 

 

7

8

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

3840 FHD F03

2

X24C16

DEVICE OPERATION

The X24C16 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C16 will be considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C16 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

SCL

SDA

DATA STABLE DATA

CHANGE

3840 FHD F06

3

X24C16

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C16 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

Figure 2. Definition of Start and Stop

The X24C16 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C16 will respond with an acknowledge after the receipt of each subsequent eight bit word.

In the read mode the X24C16 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C16 will continue to transmit data. If an acknowledge is not detected, the X24C16 will terminate further data transmissions. The master must then issue a stop condition to return the X24C16 to the standby power mode and place the device into a known state.

 

SCL

 

 

 

SDA

 

 

 

START BIT

 

STOP BIT

 

 

 

3840 FHD F07

Figure 3. Acknowledge Response From Receiver

 

 

SCL FROM

 

 

 

MASTER

1

8

9

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

3840 FHD F08

4

X24C16

DEVICE ADDRESSING

Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C16 this is fixed as 1010[B].

Figure 4. Slave Address

HIGH

ORDER

DEVICE TYPE WORD

IDENTIFIER ADDRESS

 

 

 

 

 

 

 

 

 

 

1

0

1

0

A2

A1

A0

R/W

 

 

 

 

 

 

 

 

 

 

3840 FHD F09

The next three bits of the slave address field are the bank select bits. They are used by the host to toggle between the eight 256 x 8 banks of memory. These are, in effect, the most significant bits for the word address.

The next three bits of the slave address are an extension of the array’s address and are concatenated with the

Figure 5. Byte Write

eight bits of address in the word address field, providing direct access to the whole 2048 x 8 array.

Following the start condition, the X24C16 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type). Upon a correct compare the X24C16 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C16 will execute a read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24C16 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 2048 words in the array. Upon receipt of the word address the X24C16 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C16 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C16 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

SLAVE

 

 

 

 

WORD

 

 

 

 

 

 

 

 

 

 

S

 

BUS ACTIVITY: A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

ADDRESS

 

 

 

ADDRESS

 

 

 

DATA

 

MASTER

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

SDA LINE

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS ACTIVITY:

A

A

A

C

C

C

X24C16

K

K

K

3840 FHD F10

5

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