PreliminaryX24C02 Information
2K |
X24C02 |
256 x 8 Bit |
Serial E2PROM
FEATURES
•2.7V to 5.5V Power Supply
•Low Power CMOS
—Active Current Less Than 1 mA
—Standby Current Less Than 50 μA
•Internally Organized 256 x 8
•Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
•Four Byte Page Write Operation —Minimizes Total Write Time Per Byte
•High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years
•New Hardwire—Write Control Function
DESCRIPTION
The X24C02 is CMOS a 2048 bit serial E2PROM, internally organized 256 x 8. The X24C02 features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DIP, MSOP and SOIC packages.
FUNCTIONAL DIAGRAM
(8) VCC
(4)VSS
(7)WC
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START CYCLE |
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H.V. GENERATION |
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TIMING |
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(5) SDA |
START |
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& CONTROL |
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STOP |
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LOGIC |
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CONTROL |
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LOGIC |
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SLAVE ADDRESS |
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E2PROM |
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REGISTER |
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XDEC |
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(6) SCL |
LOAD |
INC |
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64 X 32 |
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+COMPARATOR |
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(3) A2 |
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WORD |
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(2) A1 |
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ADDRESS |
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COUNTER |
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(1) A0 |
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R/W |
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YDEC |
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8 |
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PIN |
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CK |
DOUT |
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DATA REGISTER |
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DOUT |
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ACK |
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3838 FHD F01 |
© Xicor, 1991 Patents Pending |
1 |
Characteristics subject to change without notice |
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3838-1.2 7/30/96 T0/C3/D1 SH
X24C02
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.
Address (A0, A1, A2)
The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven to VSS or to VCC.
Write Control (WC)
The Write Control input controls the ability to write to the device. When WC is LOW (tied to VSS) the X24C02 will be enabled to perform write operations. When WC is HIGH (tied to VCC) the internal high voltage circuitry will be disabled and all writes will be disabled.
PIN CONFIGURATION
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DIP/SOIC/MSOP |
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A0 |
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1 |
8 |
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VCC |
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A1 |
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2 |
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WC |
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X24C02 |
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A2 |
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SCL |
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VSS |
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SDA |
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3838 FHD F02 |
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PIN DESCRIPTIONS
Symbol |
Description |
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A0–A2 |
Address Inputs |
SDA |
Serial Data |
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SCL |
Serial Clock |
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WC |
Write Control |
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VSS |
Ground |
VCC |
+5V |
3838 PGM T01
2
X24C02
DEVICE OPERATION
The X24C02 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C02 will be considered a slave in all applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C02 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SCL
SDA
DATA STABLE DATA
CHANGE
3838 FHD F06
3
X24C02
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C02 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 2. Definition of Start and Stop
The X24C02 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C02 will respond with an acknowledge after the receipt of each subsequent eight bit word.
In the read mode the X24C02 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C02 will continue to transmit data. If an acknowledge is not detected, the X24C02 will terminate further data transmissions. The master must then issue a stop condition to return the X24C02 to the standby power mode and place the device into a known state.
SCL
SDA
START BIT |
STOP BIT |
3838 FHD F07
Figure 3. Acknowledge Response From Receiver
SCL FROM |
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MASTER |
1 |
8 |
9 |
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START |
ACKNOWLEDGE |
3838 FHD F08
4
X24C02
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave are the device type identifier (see Figure 4). For the X24C02 this is fixed as 1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
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1 |
0 |
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A2 |
A1 |
A0 |
R/W |
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DEVICE
ADDRESS
3838 FHD F09
The next three significant bits address a particular device. A system could have up to eight X24C02 devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs.
The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operations is selected.
Figure 5. Byte Write
Following the start condition, the X24C02 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24C02 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C02 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C02 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X24C02 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C02 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C02 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
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SLAVE |
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WORD |
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BUS ACTIVITY: A |
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ADDRESS |
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ADDRESS |
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DATA |
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MASTER |
R |
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P |
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SDA LINE |
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BUS ACTIVITY: |
A |
A |
A |
C |
C |
C |
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X24C02 |
K |
K |
K |
3838 FHD F010
Figure 6. Page Write
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SLAVE |
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WORD |
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BUS ACTIVITY: A |
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ADDRESS |
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ADDRESS (n) |
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DATA n |
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DATA n+1 |
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DATA n+3 |
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MASTER |
R |
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P |
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SDA LINE |
S |
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BUS ACTIVITY: |
A |
A |
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A |
C |
C |
C |
C |
C |
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X24C02 |
K |
K |
K |
K |
K |
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
3838 FHD F011
5