XICOR X24C01APM-3,5, X24C01APM-3, X24C01APM, X24C01API-3,5, X24C01API-3 Datasheet

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XICOR X24C01APM-3,5, X24C01APM-3, X24C01APM, X24C01API-3,5, X24C01API-3 Datasheet

PreliminaryX24C01A Information

1K

X24C01A

128 x 8 Bit

Serial E2PROM

FEATURES

2.7V to 5.5V Power Supply

Low Power CMOS

—Active Current Less Than 1 mA —Standby Current Less Than 50 μA

Internally Organized 128 x 8

Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

Four Byte Page Write Operation —Minimizes Total Write Time Per Byte

High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years

New Hardwire – Write Control Function

DESCRIPTION

The X24C01A is a CMOS 1024 bit serial E2PROM, internally organized 128 x 8. The X24C01A features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus.

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in an eight pin DIP and SOIC package.

FUNCTIONAL DIAGRAM

(8) VCC

(4) VSS

(7) WC

START CYCLE

H.V. GENERATION

TIMING

 

 

 

& CONTROL

(5) SDA

START

 

 

 

 

 

 

STOP

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

LOGIC

 

 

 

 

SLAVE ADDRESS

 

 

 

 

E2PROM

 

REGISTER

LOAD

INC

XDEC

 

(6) SCL

+COMPARATOR

 

 

32x32

(3) A2

 

WORD

 

 

 

(2) A1

 

ADDRESS

 

 

 

 

COUNTER

 

 

 

(1) A0

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

YDEC

 

 

 

 

 

 

8

 

 

 

PIN

 

CK

DOUT

 

 

 

 

 

 

 

 

 

 

DATA REGISTER

 

DOUT

 

 

 

 

 

 

ACK

 

 

 

 

 

3841 FHD F01

© Xicor, 1991 Patents Pending

1

Characteristics subject to change without notice

 

 

3841-1

X24C01A

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.

Address (A0, A1, A2)

The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven to VSS or to VCC.

WRITE CONTROL (WC)

The Write Control input controls the ability to write to the device. When WC is LOW (tied to VSS) the X24C01A will be enabled to perform write operations. When WC is HIGH (tied to VCC) the internal high voltage circuitry will be disabled and all writes will be disabled.

DEVICE OPERATION

The X24C01A supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C01A will be considered a slave in all applications.

PIN CONFIGURATION

 

 

 

DIP/SOIC

 

 

 

 

A0

 

 

 

 

 

 

 

1

8

 

VCC

 

 

 

 

A1

 

2

7

 

 

 

 

 

 

WC

 

 

A2

 

 

X24C01A

 

 

 

 

 

3

6

 

SCL

 

 

VSS

 

4

5

 

SDA

 

 

 

 

 

 

 

 

 

3841 FHD F02

 

 

 

 

 

 

 

 

PIN NAMES

Symbol

Description

 

 

A0–A2

Address Inputs

SDA

Serial Data

 

 

SCL

Serial Clock

WC

Write Control

 

 

VSS

Ground

VCC

+5V

3841 PGM T01

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C01A continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

2

X24C01A

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA

CHANGE 3841 FHD F05

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

3841 FHD F06

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C01A to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

The X24C01A will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C01A will respond with an acknowledge after the receipt of each subsequent eight bit word.

In the read mode the X24C01A will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C01A will continue to transmit data. If an acknowledge is not detected, the X24C01A will terminate further data transmissions. The master must then issue a stop condition to return the X24C01A to the standby power mode and place the device into a known state.

SCL FROM

 

 

 

MASTER

1

8

9

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE 3841 FHD F07

3

X24C01A

DEVICE ADDRESSING

Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C01A this is fixed as 1010[B].

Figure 4. Slave Address

DEVICE TYPE

IDENTIFIER

 

 

 

 

 

 

 

 

 

 

1

0

1

0

A2

A1

A0

R/W

 

 

 

 

 

 

 

 

 

 

DEVICE

ADDRESS

3841 FHD F08

The next three significant bits address a particular device. A system could have up to eight X24C01A devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs.

The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected.

Figure 5. Byte Write

Following the start condition, the X24C01A monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24C01A outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C01A will execute a read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24C01A requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 128 words of memory. Note: the most significant bit is a don’t care. Upon receipt of the word address the X24C01A responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C01A begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C01A inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.

 

S

 

 

 

 

 

T

SLAVE

WORD

 

S

BUS ACTIVITY: A

 

T

ADDRESS

ADDRESS

DATA

MASTER

R

 

 

 

O

 

T

 

 

 

P

SDA LINE

S

P

BUS ACTIVITY:

A

A

A

 

C

C

C

 

X24C01A

K

K

K

3841 FHD F09

Figure 6. Page Write

 

S

 

 

 

 

 

 

 

 

 

T

SLAVE

 

 

 

 

 

 

S

BUS ACTIVITY: A

 

 

 

 

 

 

T

ADDRESS

WORD ADDRESS n

DATA n

DATA n–1

 

DATA n+3

MASTER

R

 

 

 

 

 

 

 

O

 

T

 

 

 

 

 

 

 

P

SDA LINE

S

 

 

 

 

 

 

 

P

BUS ACTIVITY:

 

 

A

A

 

A

A

 

A

 

 

C

C

 

C

C

 

C

X24C01A

 

 

K

K

 

K

K

 

K

 

 

 

 

NOTE: In this example n = xxxx 0000 (B); x = 1 or 0

 

 

3841 FHD F10

4

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