XICOR X24C00SM-3, X24C00SI, X24C00S-3, X24C00S-2.7, X24C00S Datasheet

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APPLICATION NOTES

A V A I L A B L E

X24C00AN4 • AN12 • AN22 • AN26 • AN32

128 Bit

X24C00

16 x 8 Bit

Serial E2PROM

FEATURES

2.7V to 5.5V Power Supply

128 Bit Serial E2PROM

Low Power CMOS

—Active Current Less Than 3mA —Standby Current Less Than 50µA

Internally Organized 16 x 8

2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

Byte Mode Write

Self Timed Write Cycle

—Typical Write Cycle Time of 5ms

Push/Pull Output

High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years

Available Packages —8-Lead MSOP —8-Lead PDIP —8-Lead SOIC

DESCRIPTION

The X24C00 is a CMOS 128 bit serial E2PROM, internally organized as 16 x 8. The X24C00 features a serial interface and software protocol allowing operation on a simple two wire bus.

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

The X24C00 is fabricated with Xicor’s Advanced CMOS Floating Gate technology.

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

SCL

 

 

CONTROL

 

 

COMMAND/ADDRESS

 

 

MSOP/DIP/SOIC

 

 

 

 

 

 

 

 

1

8

 

VCC

 

 

LOGIC

 

 

REGISTER

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

2

7

 

NC

 

 

 

 

 

 

 

 

 

 

 

X24C00

 

 

 

 

 

 

 

 

 

 

NC

 

3

6

 

SCL

 

 

 

 

 

 

 

 

VSS

 

4

5

 

SDA

 

 

 

INPUT/

 

 

SHIFT REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUFFER

 

 

 

 

 

 

3836 FHD F02.1

 

 

 

 

 

 

 

 

 

 

 

MEMORY ARRAY

3836 FHD F01

© Xicor, Inc. 1991, 1995, 1996 Patents Pending

1

Characteristics subject to change without notice

3836-1.5 2/24/99 T2/C1/D0 NS

 

 

 

X24C00

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is a push/pull output and does not require the use of a pull-up resistor.

PIN NAMES

Symbol

Description

 

 

NC

No Connect

 

 

VSS

Ground

VCC

Supply Voltage

SDA

Serial Data

 

 

SCL

Serial Clock

 

 

3836 PGM T01

DEVICE OPERATION

The X24C00 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C00 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C00 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

A start may be issued to terminate the input of a control word or the input of data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are also inhibited while a write is in progress.

Stop Condition

The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is used to reset the device during a command or data input sequence and will leave the device in the standby mode. As with starts, stops are inhibited when outputting data and while a write is in progress.

Write Operation

The byte write operation is initiated with a start condition. The start condition is followed by an eight bit control byte which consists of a two bit write command (0,1), four address bits, and two “don’t care” bits (Figure 3).

2

XICOR X24C00SM-3, X24C00SI, X24C00S-3, X24C00S-2.7, X24C00S Datasheet

X24C00

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA CHANGE

3836 FHD F03

Figure 2. Definition of Start and Stop Conditions

SCL

SDA

START CONDITION

STOP CONDITION

3836 FHD F04

Figure 3. Control Byte

START C1 C2 A3 A2 A1 A0 XX XX

3836 FHD F05

3

X24C00

After receipt of the control byte, the X24C00 will enter the write mode and await the data to be written. This data is shifted into the device on the next eight SCL clocks. Once eight clocks have been received, the data in the shift register will be written into the memory array. While the write is in progress the X24C00 will not respond to any inputs. At any time prior to clocking in the last data bit, a stop command or a new start command will terminate the operation. If a start command is given, the X24C00 will reset all counters and will prepare to clock in the next control byte. If a stop command is given, the X24C00 will reset all counters and await the next start command.

At the end of the write the X24C00 will automatically reset all counters and enter the standby mode. (Figure 4).

Figure 4. Write Sequence

Read Operation

The byte read operation is initiated with a start condition. The start condition is followed by an eight-bit control byte which consists of a two-bit read command (1,0), four address bits, and two “don’t care” bits. After receipt of the control byte the X24C00 will enter the read mode and transfer data into the shift register from the array. This data is shifted out of the device on the next eight SCL clocks. At the end of the read, all counters are reset and the X24C00 will enter the standby mode. As with a write, the read operation can be interrupted by a start or stop condition while the command or address is being clocked in. While clocking data out, starts or stops cannot be generated.

During the second don’t care clock cycle, starts and stops are ignored. The master must free the bus prior to the end of this clock cycle to allow the X24C00 to begin outputting data (Figures 5 and 6).

START 0 1 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0

3836 FHD F06

Figure 5. Read Sequence

START 1 0 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0

3836 FHD F07

Figure 6. Read Cycle Timing

 

 

 

SYMBOL TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WAVEFORM

INPUTS

OUTPUTS

SCK

6

7

8

1

 

 

 

 

 

 

 

 

 

 

Must be

Will be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

steady

steady

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

May change

Will change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA IN

A0

XX

XX

 

 

 

 

 

 

 

 

 

 

 

from LOW

from LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to HIGH

to HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

May change

Will change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA OUT

 

 

 

D7 D6

 

 

 

 

 

 

 

 

 

 

from HIGH

from HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

to LOW

to LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Don’t Care:

Changing:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Changes

State Not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Allowed

Known

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N/A

Center Line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3836 FHD F08

 

 

 

 

 

 

 

 

 

 

 

Impedance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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