Preliminary Information
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64K |
X24645 |
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8192 x 8 Bit |
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Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
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FEATURES |
DESCRIPTION |
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• 2.7V to 5.5V Power Supply |
The X24645 is a CMOS 65,536-bit serial E2PROM, |
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• Low Power CMOS |
internally organized 8192 x 8. The X24645 features a |
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—Active Read Current Less Than 1mA |
serial interface and software protocol allowing opera- |
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—Active Write Current Less Than 3mA |
tion on a simple two wire bus. |
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—Standby Current Less Than 1 A |
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Two device select inputs |
(S1, S2) allow up to four |
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• Internally Organized 8192 x 8 |
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devices to share a common two wire bus. |
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• New Programmable Block Lock Protection |
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—Software Write Protection |
A Write Protect Register at the highest address loca- |
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—Programmable hardware Write Protect |
tion, 1FFFh, provides three new write protection |
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• Block Lock (0, 1/4, 1/2, or all of the E2PROM |
features: Software Write Protect, Block Write Protect, |
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array) |
and Hardware Write Protect. The Software Write |
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• 2 Wire Serial Interface |
Protect feature prevents any nonvolatile writes to the |
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• Bidirectional Data Transfer Protocol |
X24645 until the WEL bit in the write protect register is |
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• 32 Byte Page Write Mode |
set. The Block Write Protection feature allows the user |
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—Minimizes Total Write Time Per Byte |
to individually write protect four blocks of the array by |
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• Self Timed Write Cycle |
programming two bits in the write protect register. The |
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—Typical Write Cycle Time of 5ms |
Programmable Hardware Write Protect feature allows |
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• High Reliability |
the user to install the X24645 with WP tied to VCC, |
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—Endurance: 100,000 Cycles |
program the entire memory array in place, and then |
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—Data Retention: 100 Years |
enable the hardware write protection by programming |
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• Available Packages |
a WPEN bit in the write protect register. After this, |
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—8-Lead PDIP |
selected blocks of the array, including the write protect |
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—8-Lead SOIC (JEDEC) |
register itself, are permanently write protected, as long |
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—14-Lead SOIC (JEDEC) |
as WP remains HIGH. |
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—20-Lead TSSOP |
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FUNCTIONAL DIAGRAM |
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WP |
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START CYCLE |
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H.V. GENERATION |
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TIMING & |
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VCC |
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CONTROL |
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VSS |
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WRITE PROTECT |
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SDA |
START |
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REGISTER AND |
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STOP |
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LOGIC |
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LOGIC |
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CONTROL |
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LOGIC |
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SLAVE ADDRESS |
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E2PROM |
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REGISTER |
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XDEC |
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SCL |
LOAD |
INC |
256 X 256 |
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+COMPARATOR |
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WORD |
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S2 |
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ADDRESS |
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S1 |
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COUNTER |
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R/W |
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YDEC |
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8 |
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PIN |
CK |
DOUT |
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DATA REGISTER |
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DOUT |
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ACK |
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2783 ILL F01 |
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Xicor, 1995, 1996 Patents Pending |
Characteristics subject to change without notice |
2783-3.5 5/13/96 T1/C0/D0 NS |
1 |
X24645
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet.
Device Select (S1, S2)
The device select inputs (S1, S2) are used to set the first and second bits of the 8-bit slave address. This allows up to four X24645 devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS).
Write Protect (WP)
The write protect input controls the hardware write protect feature. When held LOW, hardware write protection is disabled and the X24645 can be written normally. When this input is held HIGH, and the WPEN bit in the write protect register is set HIGH, write protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the write protect register itself.
PIN NAMES
Symbol |
Description |
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S1, |
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2 |
Device Select Inputs |
S |
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SDA |
Serial Data |
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SCL |
Serial Clock |
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WP |
Write Protect |
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VSS |
Ground |
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VCC |
Supply Voltage |
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NC |
No Connect |
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2783 FRM T01.1
PIN CONFIGURATIONS
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8-LEAD DIP & SOIC |
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NC |
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1 |
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8 |
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VCC |
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S1 |
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2 |
X24645 |
7 |
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WP |
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S2 |
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6 |
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SCL |
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VSS |
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SDA |
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14-LEAD SOIC |
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NC |
NC |
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1 |
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14 |
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NC |
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2 |
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NC |
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3 |
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12 |
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VCC |
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S1 |
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4 |
X24645 |
11 |
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WP |
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SCL |
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S2 |
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5 |
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10 |
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SDA |
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VSS |
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NC |
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20-LEAD TSSOP |
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NC |
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NC |
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VCC |
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S1 |
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WP |
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NC |
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4 |
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NC |
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5 |
X24645 |
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NC |
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NC |
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15 |
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NC |
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7 |
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14 |
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SCL |
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S |
2 |
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VSS |
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SDA |
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9 |
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12 |
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NC |
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2783 ILL F02.4
2
X24645
DEVICE OPERATION
The X24645 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24645 will be considered a slave in all applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24645 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SCL
SDA
DATA STABLE DATA
CHANGE |
2783 ILL F04 |
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Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)
(6)tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT |
STOP BIT |
2783 ILL F05 |
3
X24645
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
The X24645 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24645 will respond with an acknowledge after the receipt of each subsequent 8-bit word.
In the read mode the X24645 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24645 will continue to transmit data. If an acknowledge is not detected, the X24645 will terminate further data transmissions. The master must then issue a stop condition to return the X24645 to the standby power mode and place the device into a known state.
SCL FROM |
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MASTER |
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8 |
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DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START |
ACKNOWLEDGE |
2783 ILL F06
4
X24645
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next two bits are the device select bits. A system could have up to four X24645’s on the bus. The four addresses are defined by the state of the S1 and S2 inputs. S2 of the slave address must be the inverse of
the S2 input pin.
Figure 4. Slave Address
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HIGH ORDER |
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ADDRESS |
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SELECT |
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S2 |
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S1 |
A12 |
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A11 |
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A10 |
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A9 |
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R/W |
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2783 ILL F07.1 |
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The next five bits of the slave address are an extension of the array’s address and are concatenated with the eight bits of address in the byte address field, providing direct access to the whole 8192 x 8 array.
Figure 5. Byte Write
The last bit of the slave address defines the operation to be performed. When set HIGH a read operation is selected, when set LOW, a write operation is selected.
Following the start condition, the X24645 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct compare the X24645 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24645 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24645 requires a second address field. This address field is the byte address, comprised of eight bits, providing access to any one of 8192 words in the array. Upon receipt of the byte address, the X24645 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24645 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24645 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
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SLAVE |
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BYTE |
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BUS ACTIVITY: |
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ADDRESS |
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DATA |
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MASTER |
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SDA LINE |
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BUS ACTIVITY: |
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A |
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C |
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C |
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X24645 |
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2783 ILL F08.1
5
X24645
Page Write
The X24645 is capable of a 32-byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to thirty-one more bytes. After the receipt of each byte, the X24645 will respond with an acknowledge.
After the receipt of each byte, the five low order address bits are internally incremented by one. The high order eight bits of the address remain constant. If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will “roll over” and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence.
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Flow 1.
Flow 1. ACK Polling Sequence
WRITE OPERATION |
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COMPLETED |
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ENTER ACK POLLING |
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ISSUE |
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START |
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ISSUE SLAVE |
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ISSUE STOP |
ADDRESS AND R/W = 0 |
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ACK |
NO |
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RETURNED? |
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YES |
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NEXT |
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OPERATION |
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A WRITE? |
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ISSUE BYTE |
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ISSUE STOP |
ADDRESS |
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PROCEED |
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PROCEED |
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2783 ILL F09 |
Figure 6. Page Write
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SLAVE |
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BUS ACTIVITY: |
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ADDRESS BYTE ADDRESS (n) |
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DATA n |
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DATA n+1 |
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DATA n+31 |
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MASTER |
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P |
SDA LINE |
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BUS ACTIVITY: |
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C |
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C |
|
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|
|
C |
|
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|
|
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|
C |
|
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|
C |
|||
X24645 |
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K |
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K |
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|
K |
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|
K |
|
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|
K |
2783 ILL F10.2
6