XICOR X24645VM-2,7, X24645VM, X24645VI-2,7, X24645S8I, X24645S8-2,7 Datasheet

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Preliminary Information

 

64K

X24645

 

 

 

 

8192 x 8 Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Advanced 2-Wire Serial E2PROM with Block LockTM Protection

 

FEATURES

DESCRIPTION

 

 

 

 

 

 

 

2.7V to 5.5V Power Supply

The X24645 is a CMOS 65,536-bit serial E2PROM,

Low Power CMOS

internally organized 8192 x 8. The X24645 features a

 

—Active Read Current Less Than 1mA

serial interface and software protocol allowing opera-

 

—Active Write Current Less Than 3mA

tion on a simple two wire bus.

 

—Standby Current Less Than 1 A

 

 

 

 

 

 

 

 

 

 

 

Two device select inputs

(S1, S2) allow up to four

Internally Organized 8192 x 8

devices to share a common two wire bus.

New Programmable Block Lock Protection

 

 

 

 

 

 

 

 

 

 

 

 

—Software Write Protection

A Write Protect Register at the highest address loca-

 

—Programmable hardware Write Protect

tion, 1FFFh, provides three new write protection

Block Lock (0, 1/4, 1/2, or all of the E2PROM

features: Software Write Protect, Block Write Protect,

 

array)

and Hardware Write Protect. The Software Write

2 Wire Serial Interface

Protect feature prevents any nonvolatile writes to the

Bidirectional Data Transfer Protocol

X24645 until the WEL bit in the write protect register is

32 Byte Page Write Mode

set. The Block Write Protection feature allows the user

 

—Minimizes Total Write Time Per Byte

to individually write protect four blocks of the array by

Self Timed Write Cycle

programming two bits in the write protect register. The

 

—Typical Write Cycle Time of 5ms

Programmable Hardware Write Protect feature allows

High Reliability

the user to install the X24645 with WP tied to VCC,

 

—Endurance: 100,000 Cycles

program the entire memory array in place, and then

 

—Data Retention: 100 Years

enable the hardware write protection by programming

Available Packages

a WPEN bit in the write protect register. After this,

 

—8-Lead PDIP

selected blocks of the array, including the write protect

 

—8-Lead SOIC (JEDEC)

register itself, are permanently write protected, as long

 

—14-Lead SOIC (JEDEC)

as WP remains HIGH.

 

 

 

 

 

 

 

 

—20-Lead TSSOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTIONAL DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

START CYCLE

 

H.V. GENERATION

 

 

 

 

 

 

 

 

 

 

TIMING &

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE PROTECT

 

SDA

START

 

 

REGISTER AND

 

 

STOP

 

 

LOGIC

 

 

LOGIC

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

LOGIC

 

 

 

SLAVE ADDRESS

 

 

 

E2PROM

 

REGISTER

 

 

XDEC

SCL

LOAD

INC

256 X 256

+COMPARATOR

 

 

 

 

 

 

 

WORD

 

 

S2

 

ADDRESS

 

 

S1

 

COUNTER

 

 

 

 

 

 

 

 

 

R/W

 

 

YDEC

 

 

 

 

 

8

 

 

 

PIN

CK

DOUT

 

 

 

 

 

 

 

DATA REGISTER

 

DOUT

 

 

 

 

 

ACK

 

 

 

2783 ILL F01

 

 

 

 

 

Xicor, 1995, 1996 Patents Pending

Characteristics subject to change without notice

2783-3.5 5/13/96 T1/C0/D0 NS

1

X24645

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet.

Device Select (S1, S2)

The device select inputs (S1, S2) are used to set the first and second bits of the 8-bit slave address. This allows up to four X24645 devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS).

Write Protect (WP)

The write protect input controls the hardware write protect feature. When held LOW, hardware write protection is disabled and the X24645 can be written normally. When this input is held HIGH, and the WPEN bit in the write protect register is set HIGH, write protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the write protect register itself.

PIN NAMES

Symbol

Description

 

 

 

 

S1,

 

2

Device Select Inputs

S

SDA

Serial Data

 

 

SCL

Serial Clock

 

 

WP

Write Protect

 

 

VSS

Ground

VCC

Supply Voltage

NC

No Connect

 

 

 

 

2783 FRM T01.1

PIN CONFIGURATIONS

 

 

 

8-LEAD DIP & SOIC

 

NC

 

 

 

 

 

 

 

1

 

8

 

VCC

 

 

 

 

 

 

 

S1

 

2

X24645

7

 

WP

 

 

 

 

 

 

 

 

 

 

 

S2

 

3

 

6

 

SCL

 

 

 

VSS

 

4

 

5

 

SDA

 

 

 

 

 

 

 

14-LEAD SOIC

 

 

 

 

 

 

 

 

 

NC

NC

 

1

 

14

 

NC

 

2

 

13

 

NC

NC

 

3

 

12

 

VCC

 

S1

 

4

X24645

11

 

WP

 

 

 

SCL

 

 

 

 

 

 

 

 

 

S2

 

5

 

10

 

 

 

 

 

SDA

VSS

 

6

 

9

 

 

 

 

NC

NC

 

7

 

8

 

 

 

 

 

 

 

 

 

 

 

 

20-LEAD TSSOP

 

 

 

 

 

 

 

 

 

NC

 

1

 

20

 

NC

 

 

 

 

 

 

NC

 

2

 

19

 

VCC

 

 

 

 

 

 

 

S1

 

3

 

18

 

WP

 

 

 

 

NC

 

4

 

17

 

NC

NC

 

5

X24645

16

 

NC

NC

 

6

 

15

 

NC

 

 

 

7

 

14

 

SCL

 

S

2

 

 

 

VSS

 

8

 

13

 

SDA

NC

 

9

 

12

 

NC

NC

 

10

 

11

 

NC

 

 

 

 

 

 

 

 

 

2783 ILL F02.4

2

X24645

DEVICE OPERATION

The X24645 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24645 will be considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24645 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

SCL

SDA

DATA STABLE DATA

CHANGE

2783 ILL F04

 

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)

(6)tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

2783 ILL F05

3

X24645

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

The X24645 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24645 will respond with an acknowledge after the receipt of each subsequent 8-bit word.

In the read mode the X24645 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24645 will continue to transmit data. If an acknowledge is not detected, the X24645 will terminate further data transmissions. The master must then issue a stop condition to return the X24645 to the standby power mode and place the device into a known state.

SCL FROM

 

 

 

MASTER

1

8

9

DATA OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

2783 ILL F06

4

X24645

DEVICE ADDRESSING

Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next two bits are the device select bits. A system could have up to four X24645’s on the bus. The four addresses are defined by the state of the S1 and S2 inputs. S2 of the slave address must be the inverse of

the S2 input pin.

Figure 4. Slave Address

 

DEVICE

 

 

HIGH ORDER

 

 

 

 

ADDRESS

 

 

SELECT

 

 

 

 

BITS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2

 

S1

A12

 

A11

 

A10

 

 

 

 

 

 

 

 

 

 

A9

A8

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2783 ILL F07.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The next five bits of the slave address are an extension of the array’s address and are concatenated with the eight bits of address in the byte address field, providing direct access to the whole 8192 x 8 array.

Figure 5. Byte Write

The last bit of the slave address defines the operation to be performed. When set HIGH a read operation is selected, when set LOW, a write operation is selected.

Following the start condition, the X24645 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct compare the X24645 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24645 will execute a read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24645 requires a second address field. This address field is the byte address, comprised of eight bits, providing access to any one of 8192 words in the array. Upon receipt of the byte address, the X24645 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24645 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24645 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

SLAVE

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

S

 

BUS ACTIVITY:

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

ADDRESS

 

ADDRESS

 

 

 

DATA

 

 

MASTER

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

SDA LINE

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS ACTIVITY:

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

A

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

C

 

X24645

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

K

 

2783 ILL F08.1

5

XICOR X24645VM-2,7, X24645VM, X24645VI-2,7, X24645S8I, X24645S8-2,7 Datasheet

X24645

Page Write

The X24645 is capable of a 32-byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to thirty-one more bytes. After the receipt of each byte, the X24645 will respond with an acknowledge.

After the receipt of each byte, the five low order address bits are internally incremented by one. The high order eight bits of the address remain constant. If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will “roll over” and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence.

Acknowledge Polling

The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Flow 1.

Flow 1. ACK Polling Sequence

WRITE OPERATION

 

 

 

COMPLETED

 

 

 

ENTER ACK POLLING

 

 

ISSUE

 

 

 

START

 

 

 

ISSUE SLAVE

 

 

ISSUE STOP

ADDRESS AND R/W = 0

 

 

 

ACK

NO

 

RETURNED?

 

 

 

 

YES

 

 

 

NEXT

 

NO

 

OPERATION

 

 

 

 

 

A WRITE?

 

 

 

YES

 

 

 

ISSUE BYTE

 

 

ISSUE STOP

ADDRESS

 

 

PROCEED

 

 

PROCEED

 

 

 

2783 ILL F09

Figure 6. Page Write

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

SLAVE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

BUS ACTIVITY:

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

ADDRESS BYTE ADDRESS (n)

 

 

DATA n

 

 

DATA n+1

 

DATA n+31

 

MASTER

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

SDA LINE

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS ACTIVITY:

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

X24645

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

2783 ILL F10.2

6

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