XICOR X24321S8I-2,5, X24321S8I-1,8, X24321S8I, X24321S8-2,5, X24321S8-1,8 Datasheet

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32K

X24321

4K x 8 Bit

400 KHz 2-Wire Serial E2PROM

FEATURES

1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power Supply Operation

Low Power CMOS

—Active Read Current Less Than 1mA

—Active Write Current Less Than 3mA —Standby Current Less Than 1 A

400KHz Fast Mode 2-Wire Serial Interface —Down to 1.8V

—Schmitt Trigger Input Noise Suppression —Output Slope Control for Ground Bounce

Noise Elimination

Internally Organized 4K x 8 Bit

32 Byte Page Write Mode —Minimizes Total Write Time Per Byte

Hardware Write Protect

Bidirectional Data Transfer Protocol

Self-Timed Write Cycle —Typical Write Cycle Time of 5ms

High Reliability —Endurance: 1,000,000 Cycles —Data Retention: 100 Years

8-Lead SOIC

DESCRIPTION

The X24321 is a CMOS Serial E2PROM Memory, internally organized 4K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. The bus operates at 400KHz all the way down to 1.8V.

Three device select inputs (S0–S2) allow up to eight devices to share a common two wire bus.

Hardware Write Protection is provided through a Write Protect (WP) input pin on the X24321. When the WP pin is HIGH, the upper quadrant of the Serial E2PROM array is protected against any nonvolatile write attempts.

Xicor Serial E2PROM Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

FUNCTIONAL DIAGRAM

SERIAL E2PROM DATA

 

 

 

 

 

 

DATA REGISTER

 

AND ADDRESS (SDA)

 

 

 

 

 

 

Y DECODE LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

COMMAND

 

 

 

 

 

 

 

 

DECODE

 

 

 

PAGE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AND

 

 

 

DECODE

 

 

 

 

 

 

CONTROL

 

 

 

LOGIC

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E2PROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARRAY

 

S2

DEVICE

 

 

 

WRITE

 

4K x 8

 

 

 

 

 

 

 

 

 

 

S1

SELECT

 

 

 

PROTECT

 

 

 

 

 

 

LOGIC

 

 

 

LOGIC

 

 

 

 

S0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

 

 

 

 

 

 

WRITE VOLTAGE

 

 

 

 

 

 

 

 

CONTROL

7040 FM 01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Xicor, 1995, 1996 Patents Pending

 

1

 

 

 

 

Characteristics subject to change without notice

7040 3/27/97 T0/C0/D0 SH

 

 

 

 

 

 

 

X24321

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet.

Device Select (S0, S1, S2)

The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels.

Write Protect (WP)

The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled and the device can be written normally. When this input is held HIGH, Write Protection is enabled, and nonvolatile writes are disabled to the upper quadrant of the E2PROM array.

PIN NAMES

Symbol

 

 

Description

 

 

 

 

 

 

 

 

S0, S1, S2

 

Device Select Inputs

 

SDA

 

Serial Data

 

 

 

 

 

 

 

 

SCL

 

Serial Clock

 

 

 

 

 

 

 

 

WP

 

Write Protect

 

 

 

 

 

 

 

 

VSS

 

Ground

 

VCC

 

Supply Voltage

 

 

 

 

 

 

7040 FRM T01

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

8-LEAD SOIC

 

 

 

S0

 

 

 

 

 

 

1

8

 

V

 

 

 

 

S1

 

 

 

 

CC

 

2

7

 

WP

S2

 

 

X24321

 

 

 

 

3

6

 

SCL

 

 

VSS

 

4

5

 

SDA

 

 

 

 

 

 

 

7040 FM 02

 

 

 

 

 

 

 

2

XICOR X24321S8I-2,5, X24321S8I-1,8, X24321S8I, X24321S8-2,5, X24321S8-1,8 Datasheet

X24321

DEVICE OPERATION

The device supports a bidirectional, bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the device will be considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

SCL

SDA

DATA STABLE DATA

CHANGE

7040 FM 03

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

7040 FM 04

3

X24321

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a Write Operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent byte.

In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the device to the standby power mode and place the device into a known state.

SCL FROM

 

 

 

MASTER

1

8

9

DATA OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

7040 FM 05

4

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