XICOR X24165PI, X24165P-2,7, X24165P, X24165V, X24165SM-2,7 Datasheet

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XICOR X24165PI, X24165P-2,7, X24165P, X24165V, X24165SM-2,7 Datasheet

Preliminary Information

16K

X24165

2048 x 8 Bit

Advanced 2-Wire Serial E2PROM with Block LockTM Protection

FEATURES

2.7V to 5.5V Power Supply

Low Power CMOS

—Active Read Current Less Than 1mA

—Active Write Current Less Than 3mA —Standby Current Less Than 1 A

Internally Organized 2048 x 8

New Programmable Block Lock Protection —Software Write Protection —Programmable Hardware Write Protect

Block Lock (0, 1/4, 1/2, or all of the E2PROM array)

2 Wire Serial Interface

Bidirectional Data Transfer Protocol

32 Byte Page Write Mode —Minimizes Total Write Time Per Byte

Self Timed Write Cycle

—Typical Write Cycle Time of 5ms

High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years

Available Packages —8-Lead PDIP —8-Lead SOIC (JEDEC) —14-Lead TSSOP

DESCRIPTION

The X24165 is a CMOS 16,384 bit serial E2PROM, internally organized 2048 x 8. The X24165 features a serial interface and software protocol allowing operation on a simple two wire bus.

Three device select inputs (S0, S1, S2) allow up to eight devices to share a common two wire bus.

A Write Protect Register at the highest address location, 7FFh, provides three new write protection features: Software Write Protect, Block Write Protect, and Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the X24165 until the WEL bit in the write protect register is set. The Block Write Protection feature allows the user to individually write protect four blocks of the array by programming two bits in the write protect register. The Programmable Hardware Write Protect feature allows the user to install the X24165 with WP tied to VCC, program the entire memory array in place, and then enable the hardware write protection by programming a WPEN bit in the write protect register. After this, selected blocks of the array, including the write protect register itself, are permanently write protected.

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.

FUNCTIONAL DIAGRAM

WP

 

 

 

 

 

 

 

 

 

START CYCLE

 

H.V. GENERATION

 

 

 

 

 

 

TIMING &

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE PROTECT

 

SDA

START

 

 

REGISTER AND

 

 

STOP

 

 

LOGIC

 

 

LOGIC

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

LOGIC

 

 

 

SLAVE ADDRESS

 

 

 

E2PROM

 

REGISTER

 

 

XDEC

SCL

LOAD

INC

64 X 256

+COMPARATOR

 

 

 

 

 

S2

 

WORD

 

 

S1

 

ADDRESS

 

 

 

COUNTER

 

 

S0

 

 

 

 

 

 

 

 

 

 

R/W

 

 

YDEC

 

 

 

 

 

8

 

 

 

PIN

CK

DOUT

 

 

 

 

 

 

 

DATA REGISTER

 

DOUT

 

 

 

 

 

ACK

 

 

 

6551 ILL F01.1

 

 

 

 

 

Xicor, 1995, 1996 Patents Pending

1

Characteristics subject to change without notice

6551-2.5 5/13/96 T1/C10/D0 NS

 

 

 

X24165

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the PullUp Resistor selection graph at the end of this data sheet.

Device Select (S0, S1, S2)

The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight X24165’s to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS).

Write Protect (WP)

The write protect input controls the hardware write protect feature. When held LOW, hardware write protection is disabled and the X24165 can be written normally. When this input is held HIGH, and the WPEN bit in the write protect register is set HIGH, write protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the write protect register itself.

PIN NAMES

Symbol

Description

 

 

 

 

S0,

 

1, S2

Device Select Inputs

S

SDA

Serial Data

 

 

SCL

Serial Clock

 

 

WP

Write Protect

 

 

VSS

Ground

VCC

Supply Voltage

NC

No Connect

 

 

 

 

6551 FRM T01.2

PIN CONFIGURATIONS

 

 

 

 

8-LEAD DIP & SOIC

 

 

 

 

 

 

 

 

 

 

 

S0

 

1

8

 

VCC

 

 

 

 

 

S

1

 

2

7

 

WP

 

 

 

 

 

 

 

 

X24165

 

 

 

S2

 

3

6

 

SCL

 

 

VSS

 

4

5

 

SDA

 

 

 

 

 

 

 

14-LEAD TSSOP

 

 

 

 

 

 

 

 

S0

 

1

14

 

VCC

 

S

1

 

2

13

 

WP

NC

 

3

12

 

NC

NC

 

4

X24165 11

 

NC

NC

 

5

10

 

NC

 

S2

 

6

9

 

SCL

VSS

 

7

8

 

SDA

6551 ILL F02.5

2

X24165

DEVICE OPERATION

The X24165 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24165 will be considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24165 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

SCL

SDA

DATA STABLE DATA

CHANGE

6551 ILL F04

 

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)

(6)tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

6551 ILL F05

3

X24165

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

The X24165 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24165 will respond with an acknowledge after the receipt of each subsequent eight-bit word.

In the read mode the X24165 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24165 will continue to transmit data. If an acknowledge is not detected, the X24165 will terminate further data transmissions. The master must then issue a stop condition to return the X24165 to the standby power mode and place the device into a known state.

SCL FROM

 

 

 

MASTER

1

8

9

DATA OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

6551 ILL F06

4

X24165

DEVICE ADDRESSING

Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next three bits are the device select bits. A system could have up to eight X24165’s on the bus. The eight addresses are defined by the state of the S0, S1 and S2 inputs. S1 of the slave address must be the inverse

of the S1 input pin.

Figure 4. Slave Address

DEVICE

 

 

 

 

 

HIGH ORDER

 

TYPE

DEVICE

 

WORD

 

IDENTIFIER

SELECT

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

S2

 

S1

 

S0

 

A10

 

 

 

 

 

 

 

 

 

 

 

A9

A8

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6551 ILL F07.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The next three bits of the slave address are an extension of the array’s address and are concatenated with the eight bits of address in the word address field, providing direct access to the whole 2048 x 8 array.

The last bit of the slave address defines the operation to be performed. When set HIGH a read operation is selected, when set LOW a write operation is selected.

Following the start condition, the X24165 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct compare the X24165 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24165 will execute a read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24165 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of 2048 words in the array. Upon receipt of the word address, the X24165 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24165 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24165 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.

Figure 5. Byte Write

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

SLAVE

 

 

WORD

 

 

 

 

 

 

 

 

 

 

S

 

BUS ACTIVITY:

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

ADDRESS

 

ADDRESS

 

 

 

DATA

 

 

MASTER

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

SDA LINE

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS ACTIVITY:

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

A

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

C

 

X24165

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

K

 

6551 ILL F08

5

X24165

Page Write

The X24165 is capable of a 32 byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the X24165 will respond with an acknowledge.

After the receipt of each word, the five low order address bits are internally incremented by one. The high order bits of the word address remain constant. If the master should transmit more than 32 words prior to generating the stop condition, the address counter will “roll over” and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.

Acknowledge Polling

The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Flow 1.

Flow 1. ACK Polling Sequence

WRITE OPERATION

 

 

 

COMPLETED

 

 

 

ENTER ACK POLLING

 

 

ISSUE

 

 

 

START

 

 

 

ISSUE SLAVE

 

 

ISSUE STOP

ADDRESS AND R/W = 0

 

 

 

ACK

NO

 

RETURNED?

 

 

 

 

YES

 

 

 

NEXT

 

NO

 

OPERATION

 

 

 

 

 

A WRITE?

 

 

 

YES

 

 

 

ISSUE BYTE

 

 

ISSUE STOP

ADDRESS

 

 

PROCEED

 

 

PROCEED

 

 

 

6551 ILL F09

Figure 6. Page Write

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

SLAVE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

BUS ACTIVITY:

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

ADDRESS WORD ADDRESS (n)

 

 

DATA n

 

 

DATA n+1

 

DATA n+31

 

MASTER

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

SDA LINE

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS ACTIVITY:

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

C

X24165

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

K

6551 ILL F10.1

6

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