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128K |
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X24128 |
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16K x 8 Bit |
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400KHz 2-Wire Serial E2PROM with Block LockTM |
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FEATURES |
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DESCRIPTION |
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• Save Critical Data with Programmable |
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The X24128 is a CMOS Serial E2PROM, internally |
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Block Lock Protection |
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organized 16K x 8. The device features a serial inter- |
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—Block Lock (0, 1/4, 1/2, or all of E2PROM Array) |
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face and software protocol allowing operation on a |
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—Software Write Protection |
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simple two wire bus. |
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—Programmable Hardware Write Protect |
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Three device select inputs (S0–S2) allow up to eight |
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• In Circuit Programmable ROM Mode |
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• 400KHz 2-Wire Serial Interface |
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devices to share a common two wire bus. |
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—Schmitt Trigger Input Noise Suppression |
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A Write Protect Register at the highest address loca- |
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—Output Slope Control for Ground Bounce |
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tion, FFFFh, provides three write protection features: |
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Noise Elimination |
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Software Write Protect, Block Lock Protect, and |
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• Longer Battery Life With Lower Power |
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Programmable Hardware Write Protect. The Software |
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—Active Read Current Less Than 1mA |
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Write Protect feature prevents any nonvolatile writes to |
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—Active Write Current Less Than 3mA |
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the device |
until the WEL bit in the Write Protect |
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—Standby Current Less Than 1 A |
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Register is set. The Block Lock Protection feature |
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• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V |
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gives the user four array block protect options, set by |
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Power Supply Versions |
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programming two bits in the Write Protect Register. |
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• 32 Word Page Write Mode |
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The Programmable Hardware Write Protect feature |
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—Minimizes Total Write Time Per Word |
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allows the user to install the device with WP tied to |
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• Internally Organized 16K x 8 |
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VCC, write to and Block Lock the desired portions of |
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• Bidirectional Data Transfer Protocol |
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the memory array in circuit, and then enable the In |
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• Self-Timed Write Cycle |
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Circuit Programmable ROM Mode by programming the |
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—Typical Write Cycle Time of 5ms |
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WPEN bit HIGH in the Write Protect Register. After |
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• High Reliability |
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this, the Block Locked portions of the array, including |
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—Endurance: 100,000 Cycles |
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Protect Register itself, are permanently |
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—Data Retention: 100 Years |
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protected from being erased. |
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• 14-Lead SOIC |
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• 16-Lead SOIC |
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• 8-Lead PDIP |
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FUNCTIONAL DIAGRAM |
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SERIAL E2PROM DATA |
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DATA REGISTER |
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AND ADDRESS (SDA) |
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Y DECODE LOGIC |
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SERIAL E2PROM |
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SCL |
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COMMAND |
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DECODE |
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PAGE |
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ARRAY |
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AND |
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DECODE |
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16K x 8 |
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CONTROL |
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LOGIC |
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LOGIC |
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4K x 8 |
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BLOCK LOCK AND |
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WRITE PROTECT |
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CONTROL LOGIC |
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4K x 8 |
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S2 |
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DEVICE |
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WRITE |
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S1 |
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SELECT |
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PROTECT |
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S0 |
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LOGIC |
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REGISTER |
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8K x 8 |
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WP |
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WRITE VOLTAGE |
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CONTROL |
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7027 FM 01 |
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Xicor, 1995, 1996 Patents Pending |
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1 |
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Characteristics subject to change without notice |
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7027-1.3 5/14/97 T2/C0/D2 SH |
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X24128
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-up resistor selection graph at the end of this data sheet.
Device Select (S0, S1, S2)
The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS).
Write Protect (WP)
The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set HIGH, the Write Protect Register is protected, preventing changes to the Block Lock Protection and WPEN bits.
PIN NAMES
Symbol |
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Description |
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S0, S1, S2 |
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Device Select Inputs |
SDA |
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Serial Data |
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SCL |
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Serial Clock |
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WP |
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Write Protect |
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VSS |
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Ground |
VCC |
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Supply Voltage |
NC |
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No Connect |
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7027 FM T01 |
PIN CONFIGURATION |
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.344”
.394”
.430”
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14 Lead SOIC |
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S0 |
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1 |
14 |
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V |
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S1 |
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CC |
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WP |
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12 |
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NC |
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NC |
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11 |
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NC |
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X24128 |
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NC |
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10 |
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NC |
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9 |
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SCL |
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VSS |
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8 |
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SDA |
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.244” |
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16 Lead SOIC |
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S0 |
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1 |
16 |
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V |
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S1 |
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2 |
15 |
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CC |
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WP |
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NC |
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3 |
14 |
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NC |
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NC |
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X24128 |
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NC |
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12 |
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NC |
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NC |
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NC |
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S2 |
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SCL |
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VSS |
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SDA |
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.244” |
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S0 |
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7 |
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CC |
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X24128 |
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3 |
6 |
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.325” |
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Not to scale
7027 FM 02
2
X24128
DEVICE OPERATION
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the device will be considered a slave in all applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SCL
SDA
DATA STABLE DATA
CHANGE |
7027 FM 03 |
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT |
STOP BIT |
7027 FM 04 |
3
X24128
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the device to the standby power mode and place the device into a known state.
SCL FROM |
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MASTER |
1 |
8 |
9 |
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START |
ACKNOWLEDGE |
7027 FM 05
4
X24128
DEVICE ADDRESSING
Following a start condition, the master must output the address of the slave it is accessing. The first four bits of the Slave Address Byte are the device type identifier bits. These must equal “1010”The. next 3 bits are the device select bits S0, S1, and S2. This allows up to 8 devices to share a single bus. These bits are compared to the S0, S1, and S2 device select input pins. The last bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. When it is zero then a write operation is selected. Refer to figure 4. After loading the Slave Address Byte from the SDA bus, the device compares the device type bits with the value “1010”and the device select bits with the status of the
Figure 4. Device Addressing
device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode.
The word address is either supplied by the master or obtained from an internal counter, depending on the operation. The master must supply the two Word Address Bytes as shown in figure 4.
The internal organization of the E2 array is 512 pages by 32 bytes per page. The page address is partially contained in the Word Address Byte 1 and partially in bits 7 through 5 of the Word Address Byte 0. The byte address is contained in bits 4 through 0 of the Word Address Byte 0. See figure 4.
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DEVICE TYPE |
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DEVICE |
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IDENTIFIER |
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SELECT |
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1 |
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0 |
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1 |
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0 |
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S2 |
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S1 |
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S0 |
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HIGH ORDER WORD ADDRESS |
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0 |
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0 |
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A13 |
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A11 |
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X24128 WORD ADDRESS BYTE 1 |
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LOW ORDER WORD ADDRESS |
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A4 |
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A3 |
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WORD ADDRESS BYTE 0 |
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D7 |
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DATA BYTE |
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7027 FM 06
5
X24128
WRITE OPERATIONS
Byte Write
For a write operation, the device requires the Slave Address Byte, the Word Address Byte 1, and the Word Address Byte 0, which gives the master access to any one of the words in the array. Upon receipt of the Word Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. The SDA pin is at high impedance. See figure 5.
Page Write
The device is capable of a thirty-two byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write operation after the first data word is transferred, the
master can transmit up to thirty-one more words. The device will respond with an acknowledge after the receipt of each word, and then the byte address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls ver”o and goes back to the first byte of the current page. This means that the master can write 32 words to the page beginning at any byte. If the master begins writing at byte 16, and loads 32 words, then the first 16 words are written to bytes 16 through 31, and the last 16 words are written to bytes 0 through 15. Afterwards, the address counter would point to byte 16. If the master writes more than 32 words, then the previously loaded data is overwritten by the new data, one byte at a time.
The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to figure 6 for the address, acknowledge, and data transfer sequence.
Figure 5. Byte Write Sequence
SIGNALS |
S |
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S |
T |
SLAVE |
WORD ADDRESS |
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WORD ADDRESS |
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FROM THE |
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ADDRESS |
BYTE 1 |
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BYTE 0 |
DATA |
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MASTER |
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P |
SDA BUS |
S 1 0 1 0 |
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SIGNALS |
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FROM THE |
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7027 FM 07
Figure 6. Page Write Sequence
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(0≤n≤31) |
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SLAVE |
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WORD ADDRESS |
WORD ADDRESS |
DATA |
DATA |
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FROM THE |
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ADDRESS |
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BYTE 1 |
BYTE 0 |
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(n) |
T |
MASTER |
R |
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P |
SDA BUS |
S 1 0 1 0 |
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P |
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SIGNALS |
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A |
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FROM THE |
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SLAVE |
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7027 FM 08
6