ISO 7816 Compatible
2K |
X24026 |
256 x 8 Bit |
Serial E2PROM
FEATURES
•2.7V to 5.5V Power Supply
•Low Power CMOS
—Active Current Less Than 1mA
—Standby Current Less Than 50 A
•Internally Organized 256 x 8
•Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
•Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
•High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection > 2KV
DESCRIPTION
The X24026 is a CMOS 2048 bit serial E2PROM, internally organized 256 x 8. The X24026 features a serial interface and software protocol allowing operation on a simple two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DICE form with ISO 7816 compatible pinout.
FUNCTIONAL DIAGRAM |
|
|
|
|
|
|
|
VCC |
|
|
|
|
|
|
|
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
START CYCLE |
H.V. GENERATION |
|
|
|
|
|
|
TIMING |
||
|
|
|
|
|
|
||
SDA |
START |
|
|
|
|
& CONTROL |
|
|
|
|
|
|
|
||
|
STOP |
|
|
|
|
|
|
|
LOGIC |
|
|
|
|
|
|
|
|
|
CONTROL |
|
|
|
|
|
|
|
LOGIC |
|
|
|
|
|
SLAVE ADDRESS |
|
|
|
XDEC |
E2 |
PROM |
|
REGISTER |
LOAD |
INC |
|
64 X 32 |
||
SCL |
+COMPARATOR |
|
|
||||
|
|
|
|
||||
|
|
WORD |
|
|
|
|
|
|
|
ADDRESS |
|
|
|
|
|
|
|
COUNTER |
|
|
|
|
|
|
|
R/W |
|
|
|
YDEC |
|
|
|
|
|
|
|
|
8 |
|
|
|
PIN |
|
|
CK |
DOUT |
|
|
|
|
|
|
||
|
|
|
|
|
DATA REGISTER |
||
|
DOUT |
|
|
|
|
|
|
|
ACK |
|
|
|
|
|
|
|
|
|
|
|
|
|
7020 FRM 01 |
Xicor, Inc. 1994, 1995, 1996 Patents Pending |
|
|
1 |
|
Characteristics subject to change without notice |
||
7020-1.2 2/24/97 T1/C0/D2 SH |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
X24026
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.
DIE CONFIGURATION
VSS VCC
SCL
SDA SDA
X24026 Die Revision A |
||
|
.055 x .079 |
|
|
|
7020 FRM 02 |
|
|
|
PIN DESCRIPTIONS |
|
|
|
|
|
Symbol |
|
Description |
|
|
|
SDA |
|
Serial Data |
|
|
|
SCL |
|
Serial Clock |
|
|
|
VSS |
|
Ground |
VCC |
|
+5V |
7020 FRM T01
2
X24026
DEVICE OPERATION
The X24026 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24026 will be considered a slave in all applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24026 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SCL
SDA
DATA STABLE DATA
CHANGE
7020 FRM 03
3
X24026
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24026 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 2. Definition of Start and Stop
The X24026 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24026 will respond with an acknowledge after the receipt of each subsequent eight bit word.
In the read mode the X24026 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24026 will continue to transmit data. If an acknowledge is not detected, the X24026 will terminate further data transmissions. The master must then issue a stop condition to return the X24026 to the standby power mode and place the device into a known state.
SCL
SDA
START BIT |
STOP BIT |
7020 FRM 04
Figure 3. Acknowledge Response from Receiver |
|
|
|
SCL FROM |
|
|
|
MASTER |
1 |
8 |
9 |
DATA |
|
|
|
OUTPUT |
|
|
|
FROM |
|
|
|
TRANSMITTER |
|
|
|
DATA |
|
|
|
OUTPUT |
|
|
|
FROM |
|
|
|
RECEIVER |
|
|
|
|
START |
|
ACKNOWLEDGE |
7020 FRM 05
4
X24026
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave are the device type identifier (see Figure 4). For the X24026 this is fixed as 1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
0 |
1 |
0 |
0 |
0 |
|
0 |
|
R/W |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESERVE
ADDRESS
BITS
7020 FRM 06
The next three significant bits are reserved address bits.
The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operations is selected.
Figure 5. Byte Write
Following the start condition, the X24026 monitors the SDA bus comparing the slave address being transmitted with its slave address. Upon a correct compare the X24026 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24026 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24026 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X24026 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24026 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24026 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
|
S |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
T |
|
SLAVE |
|
|
|
WORD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S |
||||||||||||||||||||
BUS ACTIVITY: A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
T |
|||||||||||||||||||||||
ADDRESS |
|
|
ADDRESS |
|
|
|
|
DATA |
||||||||||||||||||||||||||||||||||
MASTER |
R |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
O |
|||
|
T |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P |
||
SDA LINE |
S |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BUS ACTIVITY: |
A |
A |
A |
C |
C |
C |
|
X24026 |
K |
K |
K |
7020 FRM 07
Figure 6. Page Write
|
S |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
T |
|
SLAVE |
|
|
|
WORD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S |
|||||||||||||||||||
BUS ACTIVITY: A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
T |
||||||||||||||||||||||
ADDRESS |
|
ADDRESS (n) |
|
|
|
|
DATA n |
|
|
|
DATA n+1 |
|
|
|
DATA n+3 |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
MASTER |
R |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
O |
||
SDA LINE |
T |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
S |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BUS ACTIVITY: |
A |
A |
A |
A |
A |
C |
C |
C |
C |
C |
|
X24026 |
K |
K |
K |
K |
K |
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
7020 FRM 08
5