XICOR X24022SM-3, X24022SM-2,7, X24022SM, X24022SI-3, X24022SI-2,7 Datasheet

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X24022

Serial E2PROM

DESCRIPTION

The X24022 is a CMOS 2048 bit serial E2PROM, internally organized 256 x 8. The X24022 features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus.

Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. The X24022 is available in eight pin DIP and SOIC packages.

FEATURES

• 2.7V to 5.5V Power Supply

• Low Power CMOS

—Active Current Less Than 1 mA —Standby Current Less Than 50 µA

• Internally Organized 256 x 8

• Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

• 2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

• Four Byte Page Write Operation

—Minimizes Total Write Time Per Byte

• High Reliability

—Endurance: 100,000 Cycles Per Byte —Data Retention: 100 Years

FUNCTIONAL DIAGRAM

2K X24022 256 x 8 Bit

3848 FHD F01

Preliminary Information

Pin 7 No Connect

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

+COMPARATOR

H.V. GENERATION

TIMING

& CONTROL

WORD ADDRESS COUNTER

XDEC

YDEC

OUT

ACK

PROM

64 X 32

DATA REGISTER

START CYCLE

(8) V

R/W

(4) V

(5) SDA

(6) SCL

(3) A

(2) A

(1) A

OUT

LOAD INC

3848-1

X24022

PIN CONFIGURATIONPIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.

Address (A0, A1, A

The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven to VSS or to VCC.

3848 FHD F02

PIN NAMES

Symbol Description

A0–A

Address Inputs SDA Serial Data SCL Serial Clock NC No Connect V

Ground V

+5V

3848 PGM T01

1 2 3 4

8 7 6 5

NC SCL SDA

X24022

DIP/SOIC

X24022

DEVICE OPERATION

The X24022 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24022 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24022 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.

Figure 1. Data Validity

3848 FHD F06

SCL

SDA

DATA STABLE DATA

CHANGE

X24022

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24022 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.

The X24022 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24022 will respond with an acknowledge after the receipt of each subsequent eight bit word.

In the read mode the X24022 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24022 will continue to transmit data. If an acknowledge is not detected, the X24022 will terminate further data transmissions. The master must then issue a stop condition to return the X24022 to the standby power mode and place the device into a known state.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT STOP BIT

3848 FHD F07

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

3848 FHD F08

X24022

BUS ACTIVITY : MASTER

SDA LINE

BUS ACTIVITY : X24022

S T A R T

SLAVE

ADDRESS

S T O P

A C K

WORD

ADDRESS

DATA

Figure 4. Slave Address

DEVICE ADDRESSING

Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24022 this is fixed as 1010[B].

The next three significant bits address a particular device. A system could have up to eight X24022 devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs.

The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected.

Following the start condition, the X24022 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24022 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24022 will execute a read or write operation.

WRITE OPERATIONS Byte Write

For a write operation, the X24022 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X24022 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24022 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24022 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.

3848 FHD F09

Figure 5. Byte Write

3848 FHD F10

101 0 A2 A1 A0 R/W

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESS

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