—Store Cycles: 1,000,000
—Data Retention: 100 Years
• Low Power Consumption
—Active: 40mA Max.
—Standby: 100µA Max.
• Infinite Array Recall, RAM Read and Write Cycles
• Nonvolatile Store Inhibit: V
= 3.5V Typical
CC
• Fully TTL and CMOS Compatible
• JEDEC Standard 18-Pin 300-mil DIP
• 100% Compatible with X2212
DESCRIPTION
The X22C12 is a 256 x 4 CMOS NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The NOVRAM design allows data to
be easily transferred from RAM to E2PROM (STORE)
and from E2PROM to RAM (RECALL). The STORE
operation is completed within 5ms or less and the
RECALL is completed within 1µs.
Xicor NOVRAMs are designed for unlimited write operations to the RAM, either RECALLs from E2PROM or
writes from the host. The X22C12 will reliably endure
1,000,000 STORE cycles. Inherent data retention is
greater than 100 years.
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (A0–A7)
The address inputs select a 4-bit memory location
during a read or write operation.
Chip Select (CS)
The Chip Select input must be LOW to enable read or
write operations with the RAM array. CS HIGH will place
the I/O pins in the high impedance state.
Write Enable (WE)
The Write Enable input controls the I/O buffers, determining whether a RAM read or write operation is enabled. When CS is LOW and WE is HIGH, the I/O pins
will output data from the selected RAM address locations. When both CS and WE are LOW, data presented
at the I/O pins will be written to the selected address
location.
Data In/Data Out (I/O1–I/O4)
Data is written to or read from the X22C12 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CS is HIGH or during either a store or
recall operation.
STORE
The STORE input, when LOW, will initiate the transfer of
the entire contents of the RAM array to the E2PROM
array. The WE and RECALL inputs are inhibited during
the store cycle. The store operation is completed in 5ms
or less.
A store operation has priority over RAM read/write
operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted
during a RAM write operation, the write will be immediately terminated and the store performed. The data at
the RAM address that was being written will be unknown
in both the RAM and E2PROM arrays.
RECALL
The RECALL input, when LOW, will initiate the transfer
of the entire contents of the E2PROM array to the RAM
array. The transfer of data will be completed in 1µs or
less.
An array recall has priority over RAM read/write operations and will terminate both operations when RECALL
is asserted. RECALL LOW will also inhibit the STORE
input.
Automatic Recall
Upon power-up the X22C12 will automatically recall
data from the E2PROM array into the RAM array.
Write Protection
The X22C12 has three write protect features that are
employed to protect the contents of the nonvolatile
memory.
•VCC Sense—All functions are inhibited when VCC is
<3.5V typical.
• Write Inhibit—Holding either STORE HIGH or
RECALL LOW during power-up or power-down will
prevent an inadvertent store operation and E2PROM
data integrity will be maintained.
• Noise Protection—A STORE pulse of typically less
than 20ns will not initiate a store cycle.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
LHHHOutput DataRead RAM
LLHHInput Data HighWrite “1” RAM
LLHHInput Data LowWrite “0” RAM
XHLHOutput High ZArray Recall
HXLHOutput High ZArray Recall
XHHLOutput High ZNonvolatile Store
HXHLOutput High ZNonvolatile Store
ENDURANCE AND DATA RETENTION
ParameterMin.Units
Endurance100,000Data Changes Per Bit
Store Cycles1,000,000Store Cycles
Data Retention100Years
(3)
(4)
(4)
3817 PGM T05.1
3817 PGM T06
POWER-UP TIMING
SymbolParameterMax.Units
(5)
t
PUR
(5)
t
PUW
EQUIVALENT A.C. LOAD CIRCUIT
Power-up to Read Operation100µs
Power-up to Write or Store Operation5ms
A.C. CONDITIONS OF TEST
5V
Input Pulse Levels0V to 3V
Input Rise and
Fall Times10ns
919Ω
OUTPUT
497Ω
Notes: (3) Chip is deselected but may be automatically completing a store cycle.
(4) STORE = LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed
(e.g. STORE = X).
(5) t
and t
PUR
parameters are periodically sampled and not 100% tested.
are the delays required from the time VCC is stable until the specified operation can be initiated. These
PUW
100pF
3815 FHD F09.1
Input and Output
Timing Levels1.5V
3817 PGM T07
3817 PGM T04.1
4
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