XICOR X22C10DM, X22C10DI, X22C10D, X22C10SMB, X22C10SM Datasheet

X22C10

256 Bit

X22C10

64 x 4

Nonvolatile Static RAM

FEATURES

•High Performance CMOS —120ns RAM Access Time

•High Reliability

—Store Cycles: 1,000,000 —Data Retention: 100 Years

•Low Power Consumption

—Active: 40mA Max. —Standby: 100 μA Max.

•Infinite Array Recall, RAM Read and Write Cycles

•Nonvolatile Store Inhibit: VCC = 3.5V Typical

•Fully TTL and CMOS Compatible

•JEDEC Standard 18-Pin 300-mil DIP

•100% Compatible with X2210 —With Timing Enhancements

DESCRIPTION

The X22C10 is a 64 x 4 CMOS NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (STORE) and from E2PROM to RAM (RECALL). The STORE operation is completed within 5ms or less and the RECALL is completed within 1μs.

Xicor NOVRAMs are designed for unlimited write operations to the RAM, either RECALLs from E2PROM or writes from the host. The X22C10 will reliably endure 1,000,000 STORE cycles. Inherent data retention is greater than 100 years.

	FUNCTIONAL DIAGRAM							PIN CONFIGURATION
									PLASTIC DIP
		NONVOLATILE E2PROM								CERDIP
		MEMORY ARRAY						NC	1	18	VCC
						STORE		A4	2	17	NC
								A3	3	16	A5
	A0					ARRAY
		ROW	STATIC RAM					A2	4	15	I/O4
	A1					RECALL
								A1	5	X22C10 14	I/O3
		SELECT	MEMORY ARRAY
	A2							A0	6	13	I/O2
								CS	7	12	I/01
	STORE	CONTROL				VCC		VSS	8	11	WE
						V	SS	STORE	9	10	RECALL
	RECALL	LOGIC	COLUMN
	I/O1		I/O CIRCUITS
											3815 FHD F02
	I/O2	INPUT	COLUMN SELECT
										SOIC
		DATA
	I/O3	CONTROL
								A4	1	16	VCC
			A3	A4	A5
	I/O4							A3	2	15	A5
								A2	3	14	I/O4
								A1	4	13	I/O3
										X22C10
	CS							A0	5	12	I/O2
								CS	6	11	I/O1
	WE							VSS	7	10	WE
								STORE	8	9	RECALL
						3815 FHD F01
											3815 FHD F08.1

© Xicor, Inc. 1991,1995 Patents Pending	1	Characteristics subject to change without notice
3815-2.4 7/26/96 T0/CO/D3 SH

X22C10

PIN DESCRIPTIONS AND DEVICE OPERATION

Addresses (A –A)

0 5

The address inputs select a 4-bit memory location during a read or write operation.

Chip Select (CS)

The Chip Select input must be LOW to enable read or write operations with the RAM array. CS HIGH will place the I/O pins in the high impedance state.

Write Enable (WE)

The Write Enable input controls the I/O buffers, determining whether a RAM read or write operation is enabled. When CS is LOW and WE is HIGH, the I/O pins will output data from the selected RAM address locations. When both CS and WE are LOW, data presented at the I/O pins will be written to the selected address location.

Data In/Data Out (I/O –I/O)

1 4

Data is written to or read from the X22C10 through the I/O pins. The I/O pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.

STORE

The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and RECALL inputs are inhibited during the store cycle. The store operation is completed in 5ms or less.

A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM arrays.

RECALL

The RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will be completed in 1μs or less.

An array recall has priority over RAM read/write operations and will terminate both operations when RECALL is asserted. RECALL LOW will also inhibit the STORE

input.

Automatic Recall

Upon power-up the X22C10 will automatically recall data from the E2PROM array into the RAM array.

Write Protection

The X22C10 has three write protect features that are employed to protect the contents of the nonvolatile memory.

•VCC Sense—All functions are inhibited when VCC is <3.5V typical.

•Write Inhibit—Holding either STORE HIGH or RECALL LOW during power-up or power-down will prevent an inadvertent store operation and E2PROM data integrity will be maintained.

•Noise Protection—A STORE pulse of typically less than 20ns will not initiate a store cycle.

PIN NAMES

Symbol	Description
A0–A5	Address Inputs
I/O1–I/O4	Data Inputs/Outputs
WE	Write Enable
CS	Chip Select
RECALL	Recall
STORE	Store
VCC	+5V
VSS	Ground
NC	No Connect

3815 PGM T01

2

X22C10

ABSOLUTE MAXIMUM RATINGS			–65°C to +135°C
Temperature under Bias		..................
Storage Temperature .......................			–65°C to +150°C
Voltage on any Pin with
Respect to VSS .......................................			–1V to +7V
D.C. Output Current ............................................			5mA
Lead Temperature			300°C
(Soldering, 10 seconds) ..............................
RECOMMENDED OPERATING CONDITIONS
Temperature		Min.	Max.
Commercial		0°C	+70°C
Industrial		–40°C	+85°C
Military		–55°C	+125°C

3815 PGM T12.1

COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage	Limits
X22C10	5V ±10%
	3815 PGM T13

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

			Limits
Symbol	Parameter	Min.		Max.	Units	Test Conditions
lCC	VCC Supply Current,			40	mA	CS = VIL, I/Os = Open, All Others =
	RAM Read/Write					VIH, Addresses = 0.4V/2.4V Levels @
						f = 8MHz
ISB1	VCC Standby Current			2	mA	Store or Recall Functions Not Active,
	(TTL Inputs)					I/Os = Open, All Other Inputs = VIH
ISB2	VCC Standby Current			100	μA	Store or Recall functions Not Active,
	(CMOS Inputs)					I/Os = Open, All Other Inputs =
						VCC –0.3V
ILI	Input Leakage Current			10	μA	VIN = VSS to VCC
ILO	Output Leakage Current			10	μA	VOUT = VSS to VCC
VlL(2)	Input LOW Voltage	–1		0.8	V
VIH(2)	Input HIGH Voltage	2		VCC + 1	V
VOL	Output LOW Voltage			0.4	V	IOL = 4.2mA
VOH	Output HIGH Voltage	2.4			V	IOH = –2mA

						3815 PGM T02.3
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol			Parameter	Max.	Units	Test Conditions
CI/O(1)			Input/Output Capacitance	8	pF	VI/O = 0V
C	(1)		Input Capacitance	6	pF	V = 0V
	IN					IN
						3815 PGM T03
Notes:	(1)	This parameter is periodically sampled and not 100% tested.
	(2)	VIL min. and VIH max. are for reference only and are not tested.

3

X22C10

MODE SELECTION

CE	WE	RECALL	STORE	I/O	Mode
H	X	H	H	Output High Z	Not Selected(3)
L	H	H	H	Output Data	Read RAM
L	L	H	H	Input Data HIGH	Write “1” RAM
L	L	H	H	Input Data LOW	Write “0” RAM
X	H	L	H	Output High Z	Array Recall
H	X	L	H	Output High Z	Array Recall
X	H	H	L	Output High Z	Nonvolatile Store(4)
H	X	H	L	Output High Z	Nonvolatile Store(4)

3815 PGM T05.1

ENDURANCE AND DATA RETENTION

Parameter

Min.

Units

Endurance

100,000

Data Changes Per Bit

Store Cycles

1,000,000

Store Cycles

Data Retention

100

Years

3815 PGM T06

POWER-UP TIMING

Symbol

Parameter

Max.

Units

tPUR(5)

Power-up to Read Operation

100

μs

tPUW(5)

Power-up to Write or Store Operation

5

ms

3815 PGM T07

EQUIVALENT A.C. LOAD CIRCUIT

A.C. CONDITIONS OF TEST

5V

Input Pulse Levels

0V to 3V

Input Rise and

Fall Times

10ns

919Ω

Input and Output

Timing Levels

1.5V

OUTPUT

3815 PGM T04.1

497Ω

100pF

3815 FHD F09.1

Notes: (3) Chip is deselected but may be automatically completing a store cycle.

(4)STORE = LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed

(e.g. STORE = X).

(5)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.

4