XICOR X20C17PM-55, X20C17PM-45, X20C17PM-35, X20C17PI-55, X20C17PI-45 Datasheet

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XICOR X20C17PM-55, X20C17PM-45, X20C17PM-35, X20C17PI-55, X20C17PI-45 Datasheet

APPLICATION NOTE

A V A I L A B L E

X20C17 AN56

16K

X20C17

2K x 8 Bit

High Speed AUTOSTORE™ NOVRAM

FEATURES

24-Pin Standard SRAM DIP Pinout

Fast Access Time: 35ns, 45ns, 55ns

High Reliability

Endurance: 1,000,000 Nonvolatile Store Operations

Retention: 100 Years Minimum

AUTOSTORE™ NOVRAM

Automatically Stores SRAM Data Into the

E2PROM Array When VCC Low Threshold is Detected

E 2PROM Data Automatically Recalled Into RAM Upon Power-up

Low Power CMOS

Standby: 250 μA

Infinite E2PROM Array Recall, and RAM Read and Write Cycles

DESCRIPTION

The Xicor X20C17 is a 2K x 8 NOVRAM featuring a highspeed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM) and the AUTOSTORE feature which automatically saves the RAM contents to E2PROM at power-down. The X20C17 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C17 features a compatible JEDEC approved byte-wide memory pinout for industry standard SRAMs.

The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 2.5ms or less. An automatic array recall operation reloads the contents of the E2PROM into RAM upon power-up.

Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.

PIN CONFIGURATION

 

 

PLASTIC

 

 

A7

1

24

VCC

A6

2

23

A8

A5

3

22

A9

 

A4

4

21

WE

A3

5

20

 

 

OE

A2

6

19

A10

 

 

X20C17

 

 

A1

7

18

CE

A0

8

17

I/O7

I/O0

9

16

I/O6

I/O1

10

15

I/O5

I/O2

11

14

I/O4

VSS

12

13

I/O3

2015 ILL F02.1

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.

©Xicor, Inc. 1992, 1995 Patents Pending

1

Characteristics subject to change without notice

2015-2.5 8/1/97 T1/C0/D0 SH

 

 

 

X20C17

PIN DESCRIPTIONS

Addresses (A –A )

0 10

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE.

Data In/Data Out (I/O –I/O)

0 7

Data is written to or read from the X20C17 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH.

Write Enable (WE)

The Write Enable input controls the writing of data to the static RAM.

FUNCTIONAL DIAGRAM

A3–A8

 

 

ROW

 

 

SELECT

 

 

 

CE

 

 

 

 

 

 

OE

CONTROL

 

 

 

 

 

 

WE

LOGIC

 

 

 

 

A0–A2

 

 

 

 

 

 

A9–A10

 

 

 

PIN NAMES

Symbol

Description

 

 

A0–A10

Address Inputs

I/O0–I/O7

Data Input/Output

WE

Write Enable

 

 

CE

Chip Enable

OE

Output Enable

 

 

VCC

+5V

VSS

Ground

2015 PGM T01

VCC SENSE

EEPROM ARRAY

HIGH SPEED

RECALL

2K x 8

STORE

SRAM

 

ARRAY

 

COLUMN SELECT

&

I/OS

I/O0–I/O7

2015 FHD F01.1

2

X20C17

DEVICE OPERATION

The CE, OE, and WE inputs control the X20C17 operation. The X20C17 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH.

RAM Operations

RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW. A write operation requires CE and WE to be LOW. There is no limit to the number of read or write operations performed to the RAM portion of the X20C17.

Memory Transfer Operations

There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array.

Recall operations are performed automatically upon power-up.

Store operations are performed automatically upon power-down. The store operation take a maximum of 2.5ms.

Write Protection

The X20C17 supports two methods of protecting the nonvolatile data.

—If after power-up no RAM write operations have occured, no AUTOSTORE operation can be initiated.

—VCC Sense – All functions are inhibited when VCC is 3V typical.

SYMBOL TABLE

The following symbol table provides a key to understanding the conventions used in the device timing diagrams. The diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for user’s application.

WAVEFORM INPUTS

OUTPUTS

 

 

 

 

 

 

 

 

Must be

Will be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

steady

steady

 

 

 

 

 

 

 

 

May change

Will change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from LOW

from LOW

 

 

 

 

 

 

 

 

to HIGH

to HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

May change

Will change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from HIGH

from HIGH

 

 

 

 

 

 

 

 

to LOW

to LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Don’t Care:

Changing:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Changes

State Not

 

 

 

 

 

 

 

 

Allowed

Known

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N/A

Center Line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Impedance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

X20C17

ABSOLUTE MAXIMUM RATINGS*

–65°C to +135°C

Temperature under Bias ..................

Storage Temperature .......................

–65°C to +150°C

Voltage on any Pin with

 

Respect to VSS .......................................

–1V to +7V

D.C. Output Current ...........................................

10mA

Lead Temperature (Soldering, 10 seconds) ...... 300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

 

 

 

Commercial

0°C

+70°C

Industrial

–40°C

+85°C

 

 

 

Military

–55°C

+125°C

2015 PGM T02.1

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage

Limits

 

 

X20C17

4.5V to 5.25V

 

 

 

2015 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

 

 

 

 

Limits

 

 

 

 

 

 

 

 

Symbol

Parameter

Min.

Max.

Units

Test Conditions

 

 

 

 

 

 

lCC1

VCC Current (Active)

 

100

mA

WE = VIH, CE = OE = VIL

 

 

 

 

 

 

Address Inputs = 0.4V/2.4V Levels

 

 

 

 

 

 

@ f = 20MHz, All I/Os = Open

 

 

 

 

 

 

ICC2(2)

VCC Current During

 

2.5

mA

All I/Os = Open

 

 

AUTOSTORE

 

 

 

 

ISB1

VCC Standby Current

 

10

mA

All Inputs = VIH, All I/Os = Open

 

 

(TTL Input)

 

 

 

 

ISB2

VCC Standby Current

 

250

μA

All Inputs = VCC – 0.3V

 

 

(CMOS Input)

 

 

 

All I/Os = Open

ILI

 

Input Leakage Current

 

10

μA

VIN = VSS to VCC

ILO

Output Leakage Current

 

10

μA

VOUT = VSS to VCC, CE = VIH

V

(1)

Input LOW Voltage

–1

0.8

V

 

IL

 

 

 

 

 

 

V

(1)

Input HIGH Voltage

2

V + 1

V

 

IH

 

 

CC

 

 

VOL

Output LOW Voltage

 

0.4

V

IOL = 4mA

VOH

Output HIGH Voltage

2.4

 

V

IOH = –4mA

 

 

 

 

 

 

 

 

 

 

 

2015 PGM T04.3

POWER-UP TIMING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

 

 

Max.

 

 

 

Units

 

 

 

 

 

 

 

 

 

 

tPUR(2)

 

Power-Up to RAM Operation

 

 

100

 

 

 

μs

tPUW(2)

 

Power-Up to Nonvolatile Operation

 

 

5

 

 

 

ms

 

 

 

 

 

 

 

 

 

 

 

2015 PGM T05

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

 

 

 

 

 

 

 

Symbol

 

 

Test

 

Max.

 

Units

 

Conditions

 

 

 

 

 

 

 

 

 

 

CI/O(2)

 

 

Input/Output Capacitance

 

10

 

pF

 

VI/O = 0V

C (2)

 

 

Input Capacitance

 

6

 

pF

 

V

IN

= 0V

IN

 

 

 

 

 

 

 

 

 

 

2015 PGM T06.2

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

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