XICOR X20C05PM-55, X20C05PM-45, X20C05PM-35, X20C05PI-55, X20C05J-55 Datasheet

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XICOR X20C05PM-55, X20C05PM-45, X20C05PM-35, X20C05PI-55, X20C05J-55 Datasheet

APPLICATION NOTE

A V A I L A B L E

X20C05 AN56

4K

X20C05

512 x 8

High Speed AUTOSTORE™ NOVRAM

FEATURES

Fast Access Time: 35ns, 45ns, 55ns

High Reliability

Endurance: 1,000,000 Nonvolatile Store Operations

Retention: 100 Years Minimum

Power-on Recall

E 2PROM Data Automatically Recalled Into SRAM Upon Power-up

AUTOSTORE™ NOVRAM

User Enabled Option

Automatically Stores SRAM Data Into the

E2PROM Array When VCC Low Threshold is Detected

Open Drain AUTOSTORE Status Output Pin

Software Data Protection

Locks Out Inadvertent Store Operations

Low Power CMOS

Standby: 250 μA

Infinite E2PROM Array Recall, and RAM Read and Write Cycles

Upward compatible with X20C16 (16K)

DESCRIPTION

The Xicor X20C05 is a 512 x 8 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X20C05 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C05 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs, EPROMs, and E2PROMs.

The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 5μs or less.

Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.

PIN CONFIGURATION

PLASTIC

LCC

CERDIP

PLCC

NE

1

28

VCC

NC

2

27

WE

 

 

3

26

 

 

 

 

AS

7

4

25

A8

A6

5

24

NC

A5

6

23

NC

A4

7

22

OE

 

 

A3

8

X20C05 21

NC

A2

9

20

CE

 

 

 

A1

10

19

I/O7

A0

11

18

I/O6

I/O0

12

17

I/O5

I/O1

13

16

I/O4

I/O2

14

15

I/O3

 

7

NC

 

NE

NC

CC

 

WE

 

AS

 

 

 

 

 

 

 

 

 

 

 

A

 

V

 

 

 

 

 

 

4

3

2

1

32

31

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

5

 

 

 

 

 

 

 

29

 

A8

A5

6

 

 

 

 

 

 

 

28

 

NC

A4

7

 

 

 

 

 

 

 

27

 

NC

A3

8

 

 

X20C05

 

 

26

 

NC

 

9

 

 

 

 

25

 

 

 

A2

 

 

 

 

OE

(TOP VIEW)

 

 

 

A1

10

 

 

 

 

 

 

 

24

 

NC

A0

11

 

 

 

 

 

 

 

23

 

CE

 

NC

12

 

 

 

 

 

 

 

22

 

I/O7

I/O0

13

15

16

17

18

19

21

 

I/O6

 

14

20

 

 

 

 

1

2

 

SS

NC

3

4

5

 

 

 

 

I/O

I/O

 

V

I/O

 

I/O

 

I/O

 

 

 

3827 FHD F02

 

3827 FHD F03

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.

 

 

 

 

 

©Xicor, Inc. 1991 - 1997 Patents Pending

1

Characteristics subject to change without notice

3827-2.7 7/31/97 T4/C0/D0 SH

 

X20C05

PIN DESCRIPTIONS

Addresses (A –A)

0 8

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output

Enable LOW disables a store operation regardless of the state of CE, WE, or NE.

Data In/Data Out (I/O –I/O)

0 7

Data is written to or read from the X20C05 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW.

Write Enable (WE)

The Write Enable input controls the writing of data to the RAM.

FUNCTIONAL DIAGRAM

AS

A3–A6

 

 

ROW

 

 

SELECT

CE

 

 

 

 

 

 

OE

CONTROL

 

 

 

 

 

 

WE

LOGIC

 

 

 

 

NE

 

 

 

A0–A2

 

 

 

 

 

 

A7–A8

 

 

 

Nonvolatile Enable (NE)

The Nonvolatile Enable input controls the recall function to the E2PROM array.

AUTOSTORE Output (AS)

AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold

(VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller.

PIN NAMES

Symbol

Description

 

 

A0–A8

Address Inputs

I/O0–I/O7

Data Input/Output

WE

Write Enable

 

 

CE

Chip Enable

 

 

OE

Output Enable

NE

Nonvolatile Enable

 

 

AS

AUTOSTORE Output

 

 

VCC

+5V

VSS

Ground

NC

No Connect

 

 

3827 PGM T01

VCC SENSE

EEPROM ARRAY

HIGH SPEED

RECALL

512 x 8

 

SRAM

STORE

ARRAY

 

COLUMN SELECT

&

I/OS

I/O0–I/O7

3827 FHD F01

 

2

X20C05

DEVICE OPERATION

The CE, OE, WE and NE inputs control the X20C05 operation. The X20C05 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW.

RAM Operations

RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C05.

MEMORY TRANSFER OPERATIONS

There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array.

Recall operations are performed automatically upon power-up and under host system control when NE, OE and CE are LOW and WE is HIGH. The recall operation takes a maximum of 5μs.

There are two methods of initiating a store operation. The first is the software store command. This command takes the place of the hardware store employed on the X20C04. This command is issued by entering into the special command mode: NE, CE, and WE strobe LOW while at the same time a specific address and data combination is sent to the device. This is a three step

operation: the first address/data combination is 155[H]/AA[H]; the second combination is 0AA[H]/55[H]; and the final command combination is 155[H]/33[H]. This sequence of pseudo write operations will immediately initiate a store operation. Refer to the software command timing diagrams for details on set and hold times for the various signals.

The second method of storing data is through the AUTOSTORE command. When enabled, data is automatically stored from the RAM into the E2PROM array whenever VCC falls below the preset AUTOSTORE threshold. This feature is enabled by performing the first two steps for the software store with the command combination being 155[H]/CC[H].

The AUTOSTORE feature is disabled by issuing the three step command sequence with the command combination being 155[H]/CD[H]. The AUTOSTORE feature will also be reset if VCC falls below the power-up reset threshold (approximately 3.5V) and is then raised back into the operating range.

DATA PROTECTION

The X20C05 supports two methods of protecting the nonvolatile data.

—If after power-up the AUTOSTORE feature is not enabled, no AUTOSTORE can occur.

—If after power-up no RAM write operations have occurred no store operation can be initiated. The software store and AUTOSTORE commands will be ignored.

SYMBOL TABLE

 

WAVEFORM INPUTS

OUTPUTS

 

 

 

 

 

 

 

 

Must be

Will be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

steady

steady

 

 

 

 

 

 

 

 

May change

Will change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from LOW

from LOW

 

 

 

 

 

 

 

 

to HIGH

to HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

May change

Will change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from HIGH

from HIGH

 

 

 

 

 

 

 

 

to LOW

to LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Don’t Care:

Changing:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Changes

State Not

 

 

 

 

 

 

 

 

Allowed

Known

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N/A

Center Line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Impedance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

X20C05

ABSOLUTE MAXIMUM RATINGS*

–65°C to +135°C

Temperature under Bias ..................

Storage Temperature .......................

–65°C to +150°C

Voltage on any Pin with

 

Respect to VSS .......................................

–1V to +7V

D.C. Output Current ...........................................

10mA

Lead Temperature (Soldering, 10 seconds)...... 300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

 

 

 

Commercial

0°C

+70°C

Industrial

–40°C

+85°C

 

 

 

Military

–55°C

+125°C

 

 

 

3827 PGM T02.1

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage

Limits

 

 

X20C05

5V ±10%

 

 

3827 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

 

 

 

 

 

Limits

 

 

 

 

 

 

 

 

Symbol

Parameter

Min.

Max.

Units

Test Conditions

 

 

 

 

 

 

lCC1

VCC Current (Active)

 

100

mA

NE = WE = VIH, CE = OE = VIL

 

 

 

 

 

 

 

Address Inputs = 0.4V/2.4V Levels @

 

 

 

 

 

 

 

f = 20MHz. All I/Os = Open

 

 

 

 

 

 

ICC2

VCC Current During Store

 

5

mA

All Inputs = VIH

ICC3

VCC Current During

 

2.5

mA

All I/Os = Open

 

 

 

AUTOSTORE

 

 

 

 

ISB1

VCC Standby Current

 

10

mA

CE = VIH

 

 

 

(TTL Input)

 

 

 

All Other Inputs = VIH, All I/Os = Open

ISB2

VCC Standby Current

 

250

μA

All Inputs = VCC – 0.3V

 

 

 

(CMOS Input)

 

 

 

All I/Os = Open

ILI

 

Input Leakage Current

 

10

μA

VIN = VSS to VCC

ILO

Output Leakage Current

 

10

μA

VOUT = VSS to VCC, CE = VIH

V

IL

(1)

Input LOW Voltage

–1

0.8

V

 

 

 

 

 

 

 

 

V

 

(1)

Input HIGH Voltage

2

V + 0.5

V

 

 

IH

 

 

CC

 

 

VOL

Output LOW Voltage

 

0.4

V

IOL = 4mA

VOLAS

AUTOSTORE Output

 

0.4

V

IOLAS = 1mA

VOH

Output HIGH Voltage

2.4

 

V

IOH = –4mA

 

 

 

 

 

 

 

 

 

3827 PGM T04.3

POWER-UP TIMING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

 

 

Max.

 

Units

 

 

 

 

 

 

 

 

tPUR(2)

 

Power-Up to RAM Operation

 

 

100

 

μs

tPUW(2)

 

Power-Up to Nonvolatile Operation

 

 

5

 

ms

 

 

 

 

 

 

 

 

 

3827 PGM T05

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

 

 

 

 

 

Symbol

 

 

Test

 

Max.

 

Units

 

Conditions

 

 

 

 

 

 

 

 

 

 

CI/O(2)

 

 

Input/Output Capacitance

 

10

 

pF

 

VI/O = 0V

C (2)

 

 

Input Capacitance

 

6

 

pF

 

V = 0V

IN

 

 

 

 

 

 

 

 

IN

3827 PGM T06.2

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

4

X20C05

ENDURANCE AND DATA RETENTION

 

Parameter

 

 

 

 

Min.

 

 

 

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Endurance

 

 

 

100,000

 

Data Changes Per Bit

 

Store Cycles

 

 

 

1,000,000

 

 

 

Store Cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Retention

100

 

 

 

 

Years

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3827 PGM T07.1

MODE SELECTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

WE

NE

 

OE

 

Mode

 

I/O

 

Power

 

 

 

 

 

 

 

 

 

 

 

 

 

H

X

X

 

X

 

Not Selected

Output High Z

 

Standby

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

H

 

L

 

Read RAM

Output Data

 

Active

L

L

H

 

H

 

Write “1” RAM

Input Data High

 

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

H

 

H

 

Write “0” RAM

Input Data Low

 

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

L

 

L

 

Array Recall

Output High Z

 

Active

L

L

L

 

H

 

Software Command

Input Data

 

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

H

 

H

 

Output Disabled

Output High Z

 

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

L

 

L

 

Not Allowed

Output High Z

 

Active

L

H

L

 

H

 

No Operation

Output High Z

 

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3827 PGM T09

EQUIVALENT A.C. LOAD CIRCUIT

 

A.C. CONDITIONS OF TEST

 

 

 

 

5V

 

 

 

 

 

 

Input Pulse Levels

 

 

0V to 3V

 

 

 

 

 

 

 

 

Input Rise and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

735Ω

 

 

 

Fall Times

 

 

5ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input and Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

Timing Levels

 

 

1.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3827 PGM T08.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

318Ω

30pF

 

 

 

 

 

 

 

 

 

 

 

 

3827 FHD F04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

X20C05

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)

Read Cycle Limits

 

 

X20C05-35

X20C05-45

X20C05-55

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

 

 

 

 

 

 

 

 

 

tRC

Read Cycle Time

35

 

45

 

55

 

ns

tCE

Chip Enable Access Time

 

35

 

45

 

55

ns

tAA

Address Access Time

 

35

 

45

 

55

ns

tOE

Output Enable Access Time

 

20

 

25

 

30

ns

tLZ(3)

Chip Enable to Output in Low Z

0

 

0

 

0

 

ns

tOLZ(3)

Output Enable to Output in Low Z

0

 

0

 

0

 

ns

tHZ(3)

Chip Disable to Output in High Z

 

15

 

20

 

25

ns

tOHZ(3)

Output Disable to Output in High Z

 

15

 

20

 

25

ns

tOH

Output Hold From Address Change

0

 

0

 

0

 

ns

3827 PGM T10

Read Cycle

 

tRC

 

 

ADDRESS

 

 

 

 

tCE

 

 

CE

 

 

 

 

tOE

 

 

OE

 

 

 

 

VIH

 

 

WE

tOLZ

 

tOHZ

 

 

 

tLZ

tOH

tHZ

DATA I/O

 

DATA VALID

DATA VALID

 

 

tAA

 

 

 

 

3827 FHD F05

Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ and tOHZ are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.

6

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