APPLICATION NOTE
A V A I L A B L E
X20C05 AN56
4K |
X20C05 |
512 x 8 |
High Speed AUTOSTORE™ NOVRAM
FEATURES
•Fast Access Time: 35ns, 45ns, 55ns
•High Reliability
—Endurance: 1,000,000 Nonvolatile Store Operations
—Retention: 100 Years Minimum
•Power-on Recall
—E 2PROM Data Automatically Recalled Into SRAM Upon Power-up
•AUTOSTORE™ NOVRAM
—User Enabled Option
—Automatically Stores SRAM Data Into the
E2PROM Array When VCC Low Threshold is Detected
—Open Drain AUTOSTORE Status Output Pin
•Software Data Protection
—Locks Out Inadvertent Store Operations
•Low Power CMOS
—Standby: 250 μA
•Infinite E2PROM Array Recall, and RAM Read and Write Cycles
•Upward compatible with X20C16 (16K)
DESCRIPTION
The Xicor X20C05 is a 512 x 8 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X20C05 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C05 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs, EPROMs, and E2PROMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 5μs or less.
Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.
PIN CONFIGURATION
PLASTIC |
LCC |
CERDIP |
PLCC |
NE |
1 |
28 |
VCC |
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NC |
2 |
27 |
WE |
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3 |
26 |
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AS |
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7 |
4 |
25 |
A8 |
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A6 |
5 |
24 |
NC |
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A5 |
6 |
23 |
NC |
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A4 |
7 |
22 |
OE |
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A3 |
8 |
X20C05 21 |
NC |
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A2 |
9 |
20 |
CE |
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A1 |
10 |
19 |
I/O7 |
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A0 |
11 |
18 |
I/O6 |
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I/O0 |
12 |
17 |
I/O5 |
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I/O1 |
13 |
16 |
I/O4 |
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I/O2 |
14 |
15 |
I/O3 |
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7 |
NC |
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NE |
NC |
CC |
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WE |
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AS |
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A |
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V |
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4 |
3 |
2 |
1 |
32 |
31 |
30 |
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A6 |
5 |
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29 |
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A8 |
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A5 |
6 |
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28 |
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NC |
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A4 |
7 |
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27 |
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NC |
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A3 |
8 |
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X20C05 |
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26 |
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NC |
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9 |
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25 |
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A2 |
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OE |
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(TOP VIEW) |
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A1 |
10 |
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24 |
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NC |
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A0 |
11 |
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23 |
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CE |
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NC |
12 |
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22 |
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I/O7 |
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I/O0 |
13 |
15 |
16 |
17 |
18 |
19 |
21 |
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I/O6 |
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14 |
20 |
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1 |
2 |
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SS |
NC |
3 |
4 |
5 |
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I/O |
I/O |
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V |
I/O |
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I/O |
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I/O |
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3827 FHD F02 |
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3827 FHD F03 |
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. |
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©Xicor, Inc. 1991 - 1997 Patents Pending |
1 |
Characteristics subject to change without notice |
3827-2.7 7/31/97 T4/C0/D0 SH |
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X20C05
PIN DESCRIPTIONS
Addresses (A –A)
0 8
The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of the state of CE, WE, or NE.
Data In/Data Out (I/O –I/O)
0 7
Data is written to or read from the X20C05 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to the RAM.
FUNCTIONAL DIAGRAM
AS
A3–A6 |
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ROW |
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SELECT |
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CE |
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OE |
CONTROL |
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WE |
LOGIC |
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NE |
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A0–A2 |
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A7–A8 |
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Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall function to the E2PROM array.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold
(VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller.
PIN NAMES
Symbol |
Description |
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A0–A8 |
Address Inputs |
I/O0–I/O7 |
Data Input/Output |
WE |
Write Enable |
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CE |
Chip Enable |
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OE |
Output Enable |
NE |
Nonvolatile Enable |
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AS |
AUTOSTORE Output |
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VCC |
+5V |
VSS |
Ground |
NC |
No Connect |
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3827 PGM T01
VCC SENSE
EEPROM ARRAY
HIGH SPEED |
RECALL |
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512 x 8 |
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SRAM |
STORE |
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ARRAY |
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COLUMN SELECT
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I/OS
I/O0–I/O7 |
3827 FHD F01 |
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2
X20C05
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C05 operation. The X20C05 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW.
RAM Operations
RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C05.
MEMORY TRANSFER OPERATIONS
There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array.
Recall operations are performed automatically upon power-up and under host system control when NE, OE and CE are LOW and WE is HIGH. The recall operation takes a maximum of 5μs.
There are two methods of initiating a store operation. The first is the software store command. This command takes the place of the hardware store employed on the X20C04. This command is issued by entering into the special command mode: NE, CE, and WE strobe LOW while at the same time a specific address and data combination is sent to the device. This is a three step
operation: the first address/data combination is 155[H]/AA[H]; the second combination is 0AA[H]/55[H]; and the final command combination is 155[H]/33[H]. This sequence of pseudo write operations will immediately initiate a store operation. Refer to the software command timing diagrams for details on set and hold times for the various signals.
The second method of storing data is through the AUTOSTORE command. When enabled, data is automatically stored from the RAM into the E2PROM array whenever VCC falls below the preset AUTOSTORE threshold. This feature is enabled by performing the first two steps for the software store with the command combination being 155[H]/CC[H].
The AUTOSTORE feature is disabled by issuing the three step command sequence with the command combination being 155[H]/CD[H]. The AUTOSTORE feature will also be reset if VCC falls below the power-up reset threshold (approximately 3.5V) and is then raised back into the operating range.
DATA PROTECTION
The X20C05 supports two methods of protecting the nonvolatile data.
—If after power-up the AUTOSTORE feature is not enabled, no AUTOSTORE can occur.
—If after power-up no RAM write operations have occurred no store operation can be initiated. The software store and AUTOSTORE commands will be ignored.
SYMBOL TABLE
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WAVEFORM INPUTS |
OUTPUTS |
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Must be |
Will be |
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steady |
steady |
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May change |
Will change |
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from LOW |
from LOW |
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to HIGH |
to HIGH |
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May change |
Will change |
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from HIGH |
from HIGH |
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to LOW |
to LOW |
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Don’t Care: |
Changing: |
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Changes |
State Not |
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Allowed |
Known |
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N/A |
Center Line |
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is High |
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Impedance |
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3
X20C05
ABSOLUTE MAXIMUM RATINGS* |
–65°C to +135°C |
Temperature under Bias .................. |
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Storage Temperature ....................... |
–65°C to +150°C |
Voltage on any Pin with |
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Respect to VSS ....................................... |
–1V to +7V |
D.C. Output Current ........................................... |
10mA |
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature |
Min. |
Max. |
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Commercial |
0°C |
+70°C |
Industrial |
–40°C |
+85°C |
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Military |
–55°C |
+125°C |
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3827 PGM T02.1
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage |
Limits |
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X20C05 |
5V ±10% |
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3827 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
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Limits |
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Symbol |
Parameter |
Min. |
Max. |
Units |
Test Conditions |
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lCC1 |
VCC Current (Active) |
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100 |
mA |
NE = WE = VIH, CE = OE = VIL |
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Address Inputs = 0.4V/2.4V Levels @ |
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f = 20MHz. All I/Os = Open |
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ICC2 |
VCC Current During Store |
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5 |
mA |
All Inputs = VIH |
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ICC3 |
VCC Current During |
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2.5 |
mA |
All I/Os = Open |
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AUTOSTORE |
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ISB1 |
VCC Standby Current |
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10 |
mA |
CE = VIH |
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(TTL Input) |
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All Other Inputs = VIH, All I/Os = Open |
ISB2 |
VCC Standby Current |
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250 |
μA |
All Inputs = VCC – 0.3V |
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(CMOS Input) |
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All I/Os = Open |
ILI |
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Input Leakage Current |
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10 |
μA |
VIN = VSS to VCC |
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ILO |
Output Leakage Current |
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10 |
μA |
VOUT = VSS to VCC, CE = VIH |
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V |
IL |
(1) |
Input LOW Voltage |
–1 |
0.8 |
V |
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V |
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(1) |
Input HIGH Voltage |
2 |
V + 0.5 |
V |
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IH |
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CC |
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VOL |
Output LOW Voltage |
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0.4 |
V |
IOL = 4mA |
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VOLAS |
AUTOSTORE Output |
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0.4 |
V |
IOLAS = 1mA |
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VOH |
Output HIGH Voltage |
2.4 |
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V |
IOH = –4mA |
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3827 PGM T04.3 |
POWER-UP TIMING |
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Symbol |
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Parameter |
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Max. |
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Units |
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tPUR(2) |
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Power-Up to RAM Operation |
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100 |
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μs |
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tPUW(2) |
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Power-Up to Nonvolatile Operation |
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5 |
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ms |
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3827 PGM T05 |
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. |
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Symbol |
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Test |
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Max. |
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Units |
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Conditions |
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CI/O(2) |
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Input/Output Capacitance |
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10 |
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pF |
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VI/O = 0V |
C (2) |
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Input Capacitance |
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6 |
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pF |
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V = 0V |
IN |
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IN |
3827 PGM T06.2
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
4
X20C05
ENDURANCE AND DATA RETENTION
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Parameter |
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Min. |
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Units |
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Endurance |
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100,000 |
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Data Changes Per Bit |
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Store Cycles |
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1,000,000 |
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Store Cycles |
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Data Retention |
100 |
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Years |
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3827 PGM T07.1 |
MODE SELECTION |
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CE |
WE |
NE |
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OE |
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Mode |
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I/O |
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Power |
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H |
X |
X |
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Not Selected |
Output High Z |
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Standby |
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L |
H |
H |
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L |
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Read RAM |
Output Data |
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Active |
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L |
L |
H |
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H |
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Write “1” RAM |
Input Data High |
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Active |
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L |
L |
H |
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H |
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Write “0” RAM |
Input Data Low |
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Active |
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L |
H |
L |
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L |
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Array Recall |
Output High Z |
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Active |
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L |
L |
L |
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H |
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Software Command |
Input Data |
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Active |
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L |
H |
H |
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H |
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Output Disabled |
Output High Z |
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Active |
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L |
L |
L |
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Not Allowed |
Output High Z |
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Active |
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L |
H |
L |
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No Operation |
Output High Z |
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Active |
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3827 PGM T09 |
EQUIVALENT A.C. LOAD CIRCUIT |
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A.C. CONDITIONS OF TEST |
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5V |
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Input Pulse Levels |
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0V to 3V |
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Input Rise and |
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735Ω |
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Fall Times |
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5ns |
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Input and Output |
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OUTPUT |
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Timing Levels |
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1.5V |
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3827 PGM T08.2 |
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318Ω |
30pF |
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3827 FHD F04 |
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5
X20C05
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
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X20C05-35 |
X20C05-45 |
X20C05-55 |
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Symbol |
Parameter |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Units |
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tRC |
Read Cycle Time |
35 |
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45 |
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55 |
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tCE |
Chip Enable Access Time |
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35 |
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45 |
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55 |
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tAA |
Address Access Time |
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35 |
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45 |
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55 |
ns |
tOE |
Output Enable Access Time |
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20 |
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25 |
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30 |
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tLZ(3) |
Chip Enable to Output in Low Z |
0 |
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0 |
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0 |
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tOLZ(3) |
Output Enable to Output in Low Z |
0 |
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0 |
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0 |
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tHZ(3) |
Chip Disable to Output in High Z |
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15 |
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20 |
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25 |
ns |
tOHZ(3) |
Output Disable to Output in High Z |
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15 |
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20 |
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25 |
ns |
tOH |
Output Hold From Address Change |
0 |
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0 |
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0 |
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ns |
3827 PGM T10
Read Cycle
|
tRC |
|
|
ADDRESS |
|
|
|
|
tCE |
|
|
CE |
|
|
|
|
tOE |
|
|
OE |
|
|
|
|
VIH |
|
|
WE |
tOLZ |
|
tOHZ |
|
|
||
|
tLZ |
tOH |
tHZ |
DATA I/O |
|
DATA VALID |
DATA VALID |
|
|
tAA |
|
|
|
|
3827 FHD F05 |
Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ and tOHZ are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
6