Preliminary Information
New Features
Repetitive Alarms &
Temperature Compensation
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X1205 |
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2-Wire™ RTC |
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Real Time Clock/Calendar |
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FEATURES |
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• Modems |
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• Real Time Clock/Calendar |
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• Network Routers, Hubs, Switches, Bridges |
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• Cellular Infrastructure Equipment |
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—Tracks time in Hours, Minutes, and Seconds |
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• Fixed Broadband Wireless Equipment |
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—Day of the Week, Day, Month, and Year |
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• Pagers / PDA |
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PRELIMINARY |
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• 2 Polled Alarms (Non-volatile) |
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• POS Equipment |
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—Settable on the Second, Minute, Hour, Day of |
• Test Meters / Fixtures |
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the Week, Day, or Month |
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• Office Automation (Copiers, Fax) |
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—Repeat Mode (periodic interrupts) |
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• Home Appliances |
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• Oscillator Compensation on chip |
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• Computer Products |
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—Internal feedback resistor and compensation |
• Other Industrial / Medical / Automotive |
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capacitors |
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—64 position Digitally Controlled Trim Capacitor |
DESCRIPTION |
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—6 digital frequency adjustment settings to |
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±30ppm |
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The X1205 device is a Real Time Clock with clock/ |
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• Battery Switch or Super Cap Input |
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calendar, two polled alarms, oscillator compensation, |
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• 2-Wire™ Interface interoperable with I2C* |
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and battery backup switch. |
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—400kHz data transfer rate |
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The oscillator uses an external, low-cost 32.768kHz |
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• Low Power CMOS |
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crystal. All |
compensation and |
trim components are |
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—1.25µA Operating Current (Typical) |
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integrated on the chip. This eliminates several external |
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• Small Package Options |
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discrete components |
and a trim capacitor, saving |
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—8-Lead SOIC and 8-Lead TSSOP |
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board area and component cost. |
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APPLICATIONS |
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The Real-Time Clock keeps track of time with separate |
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• Utility Meters |
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registers for Hours, |
Minutes, |
and Seconds. The |
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Calendar has separate registers for Date, Month, Year |
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• HVAC Equipment |
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and Day-of-week. The calendar is correct through |
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• Audio / Video Components |
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2099, with automatic leap year correction. |
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• Set Top Box / Television |
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BLOCK DIAGRAM |
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OSC |
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Compensation |
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32.768kHz |
X1 |
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Oscillator |
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Frequency |
1Hz |
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Timer |
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Time |
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Calendar |
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Divider |
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X2 |
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Logic |
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Keeping |
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Registers |
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(SRAM) |
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Control |
Control |
Status |
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Registers |
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Registers |
Alarm |
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Decode |
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(EEPROM) |
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SCL |
Serial |
Logic |
Mask |
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Interface |
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SDA |
Decoder |
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8 |
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Interrupt Enable |
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IRQ |
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Alarm |
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Compare
Alarm Regs
(EEPROM)
*I2C is a Trademark of Philips.
REV 1.0.9 8/29/02 www.xicor.com Characteristics subject to change without notice. 1 of 22
DESCRIPTION (continued) |
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X1, X2 |
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The powerful Dual Alarms can be set to any Clock/ |
The X1 and X2 pins are the input and output, |
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Calendar value for a match. For instance, every |
respectively, of an inverting amplifier. An external |
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minute, every Tuesday, or 5:23 AM on March 21. The |
32.768kHz quartz crystal is used with the X1205 to |
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alarms can be polled in the Status Register or provide |
supply a timebase for the real time clock. The |
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a hardware interrupt |
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(IRQ |
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Pin). |
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a repeat |
recommended crystal is a Citizen CFS206-32.768KDZF. |
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mode for the alarms allowing a periodic interrupt. |
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Internal compensation circuitry is included to form a |
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The device offers a |
backup power |
input |
pin. This |
complete oscillator circuit. Care should be taken in the |
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placement of the crystal and the layout of the circuit. |
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VBACK pin allows the device to be backed up by battery |
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Plenty |
of |
ground |
plane around the device and short |
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or SuperCap. |
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X1205 device |
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X1 and |
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X2 are highly recommended. See |
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operational from 2.7 to 5.5 volts and the clock/calendar |
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Application section for more recommendations. |
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portion of the X1205 device remains fully operational |
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down to 1.8 volts (Standby Mode). |
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Figure 1. Recommended Crystal connection |
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PIN DESCRIPTIONS |
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X1 |
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8-Pin |
SOIC |
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X1205 |
8-Pin |
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TSSOP |
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X2 |
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VBACK |
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X1 |
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1 |
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VCC |
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8 |
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SCL |
POWER CONTROL OPERATION |
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X2 |
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7 |
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VBACK |
VCC |
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7 |
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SDA |
The power control circuit accepts a VCC and a VBACK |
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IRQ |
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3 |
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6 |
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SCL |
X1 |
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6 |
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VSS |
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VSS |
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SDA |
X2 |
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4 |
5 |
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IRQ |
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input. The power control circuit powers the clock from |
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VBACK when VCC < VBACK - 0.2V. It will switch back to |
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NC = No internal connection |
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power the device from VCC when VCC exceeds VBACK. |
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Figure 2. Power Control |
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Serial Clock (SCL) |
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VCC |
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The SCL input is used to clock all data into and out of |
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Voltage |
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the device. The input buffer on this pin is always active |
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VBACK |
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On |
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(not gated). |
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In |
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Off |
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Serial Data (SDA) |
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SDA is a bidirectional pin used to transfer data into and |
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out of the device. It has an open drain output and may |
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be wire ORed with other open drain or open collector |
REAL TIME CLOCK OPERATION |
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outputs. The input buffer is always active (not gated). |
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The Real Time Clock (RTC) uses an external |
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An open drain output requires the use of a pull-up |
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32.768kHz quartz crystal to maintain an accurate inter- |
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resistor. The output circuitry controls the fall time of the |
nal representation of second, minute, hour, day, date, |
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output signal with the use of a slope controlled pull- |
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month, and year. The RTC has leap-year correction. |
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down. The circuit is designed for 400kHz 2-wire inter- |
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The clock also corrects for months having fewer than |
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face speeds. |
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PRELIMINARY31 days and has a bit that controls 24 hour or AM/PM |
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VBACK |
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format. When the X1205 powers up after the loss of |
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both VCC and VBACK, the clock will not operate until at |
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This input |
provides a backup supply |
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voltage to |
the |
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least one byte is written to the clock register. |
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device. VBACK supplies power to the device in the |
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event the VCC supply fails. This pin can be connected |
Reading the Real Time Clock |
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to a battery, a Supercap or tied to ground if not used. |
The RTC is read by initiating a Read command and |
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Interrupt Output – |
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specifying the address corresponding to the register of |
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IRQ |
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This is an interrupt signal output. This signal notifies a |
the Real Time Clock. The RTC Registers can then be |
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read in a Sequential Read Mode. Since the clock runs |
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host processor |
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an alarm |
has |
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occurred |
and |
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continuously and a read takes a finite amount of time, |
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requests action. It is an open drain active low output. |
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there is the possibility that the clock could change during |
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REV 1.0.9 8/29/02 |
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www.xicor.com |
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Characteristics subject to change without notice. 2 of 22 |
X1205 – Preliminary Information
the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation.
Writing to the Real Time Clock
CCR access
The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a two step process (See section “Writing to the Clock/Control Registers.”)
The time and date may be set by writing to the RTC The CCR is divided into 5 sections. These are:
registers. To avoid changing the current time by an |
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ppm to –37 ppm whenPRELIMINARYusing a 12.5 pF load crystal. |
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uncompleted write operation, the current time value is |
1. Alarm 0 (8 bytes; non-volatile) |
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loaded into a separate buffer at the falling edge of the |
2. Alarm 1 (8 bytes; non-volatile) |
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clock on the ACK bit before the RTC data input bytes, |
3. Control (4 bytes; non-volatile) |
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the clock continues to run. The new serial input data |
4. Real Time Clock (8 bytes; volatile) |
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replaces the values in the buffer. This new RTC value |
5. Status (1 byte; volatile) |
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is loaded back into the RTC Register by a stop bit at |
Each register is read and written through buffers. The |
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the end of a valid write sequence. An invalid write |
non-volatile portion (or the counter portion of the RTC) is |
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operation aborts the time update procedure and the |
updated only if RWEL is set and only after a valid write |
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contents of the buffer are discarded. After a valid write |
operation and stop bit. A sequential read or page write |
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operation the RTC will reflect the newly loaded data |
operation provides access to the contents of only one |
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beginning with the next “one second clock cycle” after |
section of the CCR per operation. Access to another sec- |
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the stop bit is written. The RTC continues to update |
tion requires a new operation. Continued reads or writes, |
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the time while an RTC register write is in progress and |
once reaching the end of a section, will wrap around to |
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the RTC continues to run during any nonvolatile write |
the start of the section. A read or write can begin at any |
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sequences. A single byte may be written to the RTC |
address in the CCR. |
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without affecting the other bytes. |
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It is not necessary to set the RWEL bit prior to writing |
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Accuracy of the Real Time Clock |
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the status register. Section 5 supports a single byte |
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The accuracy of the Real Time Clock depends on the |
read or write only. Continued reads or writes from this |
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frequency of the quartz crystal that is used as the time |
section terminates the operation. |
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base for the RTC. Since the resonant frequency of a |
The state of the CCR can be read by performing a ran- |
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crystal is temperature dependent, |
the |
RTC perfor- |
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dom read at any address in the CCR at any time. This |
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mance will also be dependent upon temperature. The |
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returns |
the contents of that register location. Addi- |
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frequency deviation of the crystal is a function of the |
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tional registers are read by performing a sequential |
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turnover temperature of the crystal from the crystal’s |
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read. The read instruction latches all Clock registers |
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nominal frequency. For example, a >20ppm frequency |
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into a |
buffer, so an update of the clock does not |
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deviation translates into an accuracy of >1 minute per |
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change the time being read. A sequential read of the |
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month. These parameters are available from the |
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CCR will not result in the output of data from the mem- |
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crystal manufacturer. Xicor’s RTC family provides on- |
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ory array. At the end of a read, the master supplies a |
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chip crystal |
compensation networks to |
adjust |
load- |
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stop condition to end the operation and free the bus. |
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capacitance |
to tune oscillator |
frequency from |
+116 |
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After a read of the CCR, the address remains at the |
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For more |
detail information |
see |
the |
Application |
previous address +1 so the user can execute a current |
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address read of the CCR and continue reading the |
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section. |
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next Register. |
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CLOCK/CONTROL REGISTERS (CCR) |
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ALARM REGISTERS |
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The Control/Clock Registers are located in an area |
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There are two alarm registers whose contents mimic the |
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accessible following a slave byte of “1101111x” and |
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reads or writes to addresses [0000h:003Fh]. The |
contents of the RTC register, but add enable bits and |
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clock/control memory map has memory addresses |
exclude the 24 hour time selection bit. The enable bits |
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from 0000h to 003Fh. The defined addresses are |
specify which registers to use in the comparison between |
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described in the Table 1. Writing to and reading from |
the Alarm and Real Time Registers. For example: |
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the undefined addresses are not recommended. |
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REV 1.0.9 8/29/02 |
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www.xicor.com |
Characteristics subject to change without notice. 3 of 22 |
X1205 – Preliminary Information
– Setting the Enable Month Bit (EMOn*) bit in combi- |
– The user can set the X1205 to alarm every Wednes- |
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nation with other enable bits and a specific alarm |
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day at 8:00 AM by setting the EDWn*, the EHRn* |
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time, the user can establish an alarm that triggers at |
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and EMNn* enable bits to ‘1’ and setting the DWAn*, |
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the same time once a year. |
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HRAn* and MNAn* Alarm registers to 8:00AM |
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*n = 0 for Alarm 0: N = 1 for Alarm 1 |
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Wednesday. |
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– A daily alarm for 9:30PM results when the EHRn* |
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When there is a match, an alarm flag is set. The occur- |
and EMNn* enable bits are set to ‘1’ and the HRAn* |
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rence of an alarm can be determined by polling the |
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and MNAn* registers are set to 9:30PM. |
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AL0 and AL1 bits or by enabling the IRQ output, using |
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it as hardware flag. |
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*n = 0 for Alarm 0: N = 1 for Alarm 1 |
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PRELIMINARY |
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The alarm enable bits are located in the MSB of the |
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particular register. When all enable bits are set to ‘0’, |
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there are no alarms. |
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Table 1. Clock/Control Memory Map |
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Name |
7 |
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6 |
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5 |
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4 |
3 |
2 |
1 |
0 |
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Default |
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Addr. |
Type |
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Reg |
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Bit |
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Range |
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003F |
Status |
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SR |
BAT |
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AL1 |
AL0 |
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0 |
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0 |
RWEL |
WEL |
RTCF |
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01h |
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0037 |
RTC (SRAM) |
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Y2K |
0 |
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0 |
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Y2K21 |
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Y2K20 |
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Y2K13 |
0 |
0 |
Y2K10 |
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20h |
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0036 |
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DW |
0 |
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0 |
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0 |
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0 |
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0 |
DY2 |
DY1 |
DY0 |
0-6 |
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00h |
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0035 |
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YR |
Y23 |
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Y22 |
Y21 |
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Y20 |
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Y13 |
Y12 |
Y11 |
Y10 |
0-99 |
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00h |
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0034 |
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MO |
0 |
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0 |
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0 |
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G20 |
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G13 |
G12 |
G11 |
G10 |
1-12 |
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00h |
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0033 |
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DT |
0 |
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0 |
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D21 |
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D20 |
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D13 |
D12 |
D11 |
D10 |
1-31 |
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00h |
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0032 |
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HR |
MIL |
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0 |
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H21 |
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H20 |
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H13 |
H12 |
H11 |
H10 |
0-23 |
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00h |
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0031 |
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MN |
0 |
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M22 |
M21 |
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M20 |
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M13 |
M12 |
M11 |
M10 |
0-59 |
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00h |
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0030 |
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SC |
0 |
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S22 |
S21 |
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S20 |
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S13 |
S12 |
S11 |
S10 |
0-59 |
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00h |
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Control |
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DTR |
0 |
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0 |
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0 |
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0 |
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0 |
DTR2 |
DTR1 |
DTR0 |
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00h |
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0012 |
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ATR |
0 |
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ATR5 |
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ATR4 |
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ATR3 |
ATR2 |
ATR1 |
ATR0 |
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00h |
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0011 |
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INT |
IM |
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AL1E |
AL0E |
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0 |
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0 |
X |
X |
X |
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00h |
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0010 |
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0 |
0 |
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0 |
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0 |
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0 |
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0 |
0 |
0 |
0 |
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00h |
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000F |
Alarm1 |
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Y2K1 |
0 |
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0 |
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A1Y2K21 |
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A1Y2K20 |
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A1Y2K13 |
0 |
0 |
A1Y2K10 |
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20h |
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(NONVOLATILE) |
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000E |
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DWA1 |
EDW1 |
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0 |
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0 |
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0 |
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0 |
DY2 |
DY1 |
DY0 |
0-6 |
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00h |
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000D |
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YRA1 |
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Unused – Default = RTC Year value – Future expansion |
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000C |
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MOA1 |
EMO1 |
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0 |
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0 |
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A1G20 |
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A1G13 |
A1G12 |
A1G11 |
A1G10 |
1-12 |
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00h |
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000B |
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DTA1 |
EDT1 |
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0 |
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A1D21 |
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A1D20 |
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A1D13 |
A1D12 |
A1D11 |
A1D10 |
1-31 |
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00h |
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000A |
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HRA1 |
EHR1 |
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0 |
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A1H21 |
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A1H20 |
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A1H13 |
A1H12 |
A1H11 |
A1H10 |
0-23 |
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00h |
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0009 |
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MNA1 |
EMN1 |
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A1M22 |
A1M21 |
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A1M20 |
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A1M13 |
A1M12 |
A1M11 |
A1M10 |
0-59 |
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00h |
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0008 |
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SCA1 |
ESC1 |
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A1S22 |
A1S21 |
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A1S20 |
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A1S13 |
A1S12 |
A1S11 |
A1S10 |
0-59 |
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00h |
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0007 |
Alarm0 |
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Y2K0 |
0 |
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0 |
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A0Y2K21 |
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A0Y2K20 |
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A0Y2K13 |
0 |
0 |
A0Y2K10 |
19/20 |
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20h |
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(NONVOLATILE) |
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0006 |
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DWA0 |
EDW0 |
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0 |
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0 |
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0 |
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0 |
DY2 |
DY1 |
DY0 |
0-6 |
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00h |
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0005 |
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YRA0 |
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Unused – Default = RTC Year value – Future expansion |
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0004 |
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MOA0 |
EMO0 |
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0 |
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0 |
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A0G20 |
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A0G13 |
A0G12 |
A0G11 |
A0G10 |
1-12 |
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00h |
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0003 |
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DTA0 |
EDT0 |
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0 |
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A0D21 |
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A0D20 |
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A0D13 |
A0D12 |
A0D11 |
A0D10 |
1-31 |
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00h |
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0002 |
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HRA0 |
EHR0 |
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0 |
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A0H21 |
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A0H20 |
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A0H13 |
A0H12 |
A0H11 |
A0H10 |
0-23 |
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00h |
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0001 |
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MNA0 |
EMN0 |
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A0M22 |
A0M21 |
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A0M20 |
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A0M13 |
A0M12 |
A0M11 |
A0M10 |
0-59 |
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00h |
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0000 |
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SCA0 |
ESC0 |
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A0S22 |
A0S21 |
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A0S20 |
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A0S13 |
A0S12 |
A0S11 |
A0S10 |
0-59 |
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00h |
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REV 1.0.9 8/29/02 |
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www.xicor.com |
Characteristics subject to change without notice. |
4 of 22 |
X1205 – Preliminary Information
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
Date of the Week Register (DW)
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete.
Table 2. Status RegisterPRELIMINARY(SR) power to the device. The bit is set regardless of
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven |
RWEL: Register Write Enable Latch—Volatile |
|
This bit is a volatile latch that powers up in the LOW |
||
days of the week. The counter advances in the cycle |
||
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical |
(disabled) state. The RWEL bit must be set to “1” prior |
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value to a specific day of the week is arbitrary and may |
to any writes to the Clock/Control Registers. Writes to |
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be decided by the system software designer. The |
RWEL bit do not cause a nonvolatile write cycle, so the |
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default value is defined as ‘0’. |
device is ready for the next operation immediately after |
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24 Hour Time |
the stop condition. A write to the CCR requires both |
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the RWEL and WEL bits to be set in a specific |
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If the MIL bit of the HR register is 1, the RTC uses a |
sequence. |
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24-hour format. If the MIL bit is 0, the RTC uses a 12- |
WEL: Write Enable Latch—Volatile |
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hour format and H21 bit functions as an AM/PM indi- |
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cator with a ‘1’ representing PM. The clock defaults to |
The WEL bit controls the access to the CCR and |
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standard time with H21=0. |
memory array during a write operation. This bit is a |
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Leap Years |
volatile latch that powers up in the LOW (disabled) |
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state. While the WEL bit is LOW, writes to the CCR or |
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Leap years add the day February 29 and are defined |
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any array address will be ignored (no acknowledge will |
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as those years that are divisible by 4. Years divisible by |
be issued after the Data Byte). The WEL bit is set by |
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100 are not leap years, unless they are also divisible |
writing a “1” to the WEL bit and zeroes to the other bits |
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by 400. This means that the year 2000 is a leap year, |
of the Status Register. Once set, WEL remains set |
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the year 2100 is not. The X1205 does not correct for |
until either reset to 0 (by writing a “0” to the WEL bit |
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the leap year in the year 2100. |
and zeroes to the other bits of the Status Register) or |
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STATUS REGISTER (SR) |
until the part powers up again. Writes to WEL bit do |
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not cause a nonvolatile write cycle, so the device is |
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The Status Register is located in the CCR memory |
ready for the next operation immediately after the stop |
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condition. |
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map at address 003Fh. This is a volatile register only |
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and is used to control the WEL and RWEL write |
RTCF: Real Time Clock Fail Bit—Volatile |
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enable latches, read two power status and two alarm |
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This bit is set to a ‘1’ after a total power failure. This is |
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bits. This register is separate from both the array and |
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the Clock/Control Registers (CCR). |
a read only bit that is set by hardware (X1205 inter- |
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nally) when the device powers up after having lost all |
Addr |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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003Fh |
BAT |
AL1 |
AL0 |
0 |
0 |
RWEL |
WEL |
RTCF |
Default |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
BAT: Battery Supply—Volatile
whether VCC or VBACK is applied first. The loss of only one of the supplies does not result in setting the RTCF bit. The first valid write to the RTC after a complete power failure (writing one byte is sufficient) resets the RTCF bit to ‘0’.
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read-only bit and is set/ reset by hardware (X1205 internally). Once the device
begins operating from VCC, the device sets this bit to “0”.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations.
REV 1.0.9 8/29/02 |
www.xicor.com |
Characteristics subject to change without notice. 5 of 22 |
X1205 – Preliminary Information
INTERRUPT CONTROL REGISTER (INT) |
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DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm |
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Interrupt Control and Status Bits (IM, AL1E, AL0E) |
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adjustment and DTR0 gives 20 ppm adjustment. |
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There are two Interrupt Control bits, Alarm 1 Interrupt |
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A range from -30ppm to +30ppm can be represented |
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Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to |
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by using three bits above. |
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specifically enable or disable the alarm interrupt signal |
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Table 3. Digital Trimming Registers |
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output |
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. The interrupts are enabled when either the |
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(IRQ) |
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AL1E and AL0E bits are set to “1”, respectively. |
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DTR Register |
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Estimated frequency |
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Two volatile bits (AL1 and AL0), associated with the two |
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DTR2 |
DTR1 |
DTR0 |
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PPM |
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alarms respectively, indicate if an alarm has happened. |
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0 |
0 |
0 |
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0 (default) |
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These bits are set on an alarm condition regardless of |
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0 |
1 |
0 |
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+10 |
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whether the IRQ interrupt is enabled. The AL1 and AL0 |
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bits in the status register are reset by the falling edge of |
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0 |
0 |
1 |
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+20 |
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the eighth clock of a read of the register containing the |
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0 |
1 |
1 |
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+30 |
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bits. |
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1 |
0 |
0 |
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0 |
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Pulse Interrupt Mode |
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1 |
1 |
0 |
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-10 |
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The pulsed interrupt mode allows for repetitive |
or |
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1 |
0 |
1 |
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-20 |
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recurring |
alarm functionality. Hence an repetitive |
or |
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1 |
1 |
1 |
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-30 |
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recurring alarm can be set for every nth second, or nth |
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minute, or nth hour, or nth date, or for the same day of |
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Analog Trimming Register (ATR) (Non-volatile) |
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the week. The pulsed interrupt mode can be consid- |
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ered a repetitive interrupt mode, with the repetition |
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Six analog trimming Bits from ATR5 to ATR0 are pro- |
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rate set by the time setting fo the alarm. |
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vided to adjust the on-chip loading capacitance range. |
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The Pulse Interrupt Mode is enabled when the IM bit is |
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The on-chip load capacitance ranges from 3.25pF to |
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18.75pF. Each bit has a different weight for capaci- |
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set. |
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tance adjustment. In addition, using a Citizen CFS-206 |
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crystal with different ATR bit combinations provides an |
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IM Bit |
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Interrupt / Alarm Frequency |
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estimated ppm range from +116ppm to -37ppm to the |
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0 |
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Single Time Event Set By Alarm |
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nominal frequency compensation. The combination of |
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digital and analog trimming can give up to +146ppm |
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1 |
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Repetitive / Recurring Time Event Set By Alarm |
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adjustment. |
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The Alarm |
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output will output a single pulse of |
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IRQ |
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The on-chip capacitance can be calculated as follows: |
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short duration (approximately 10-40ms) once the |
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alarm condition is met. If the interrupt mode bit (IM bit) |
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CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF |
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is set, then this pulse will be periodic. |
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Note that the ATR values are in two’s complement, |
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ON-CHIP OSCILLATOR COMPENSATION |
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with ATR(000000) = 11.0pF, so the entire range runs |
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from 3.25pF to 18.75pF in 0.25pF steps. |
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Digital Trimming Register (DTR) — DTR2, DTR1 |
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The values calculated above are typical, and total load |
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and DTR0 (Non-Volatile) |
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capacitance seen by the crystal will include approxi- |
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PRELIMINARY |
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The digital trimming Bits DTR2, DTR1 and DTR0 |
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mately 2pF of package and board capacitance in addi- |
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adjust the number of counts per second and average |
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tion to the ATR value. |
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the ppm error to achieve better accuracy. |
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See Application section and Xicor’s Application Note |
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DTR2 is a sign bit. DTR2=0 means frequency |
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AN154 for more information. |
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compensation is > 0. DTR2=1 means frequency |
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compensation is < 0. |
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REV 1.0.9 8/29/02 |
www.xicor.com |
Characteristics subject to change without notice. 6 of 22 |
WRITING TO THE CLOCK/CONTROL REGISTERS |
Clock and Data |
||
Changing any of the nonvolatile bits of the clock/con- |
Data states on the SDA line can change only during |
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SCL LOW. SDA state changes during SCL HIGH are |
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trol register requires the following steps: |
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reserved for indicating start and stop conditions. See |
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– Write a 02h to the Status Register to set the Write |
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Figure 3. |
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Enable Latch (WEL). This is a volatile operation, so |
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||
there is no delay after the write. (Operation pre- |
Start Condition |
||
ceeded by a start and ended with a stop). |
All commands are preceded by the start condition, |
||
– Write a 06h to the Status Register to set both the |
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which is a HIGH to LOW transition of SDA when SCL |
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Register Write Enable Latch (RWEL) and the WEL |
is HIGH. The device continuously monitors the SDA |
||
bit. This is also a volatile cycle. The zeros in the data |
and SCL lines for the start condition and will not |
||
byte are required. (Operation preceeded by a start |
respond to any command until this condition has been |
||
and ended with a stop). |
met. See Figure 4. |
||
– Write one to 8 bytes to the Clock/Control Registers |
Stop Condition |
||
with the desired clock, alarm, or control data. This |
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sequence starts with a start bit, requires a slave byte |
All communications must be terminated by a stop |
||
of “11011110” and an address within the CCR and is |
condition, which is a LOW to HIGH transition of SDA |
||
terminated by a stop bit. A write to the CCR changes |
when SCL is HIGH. The stop condition is also used to |
||
nonvolatile register values so these initiate a non- |
place the device into the Standby power mode after a |
||
volatile write cycle and will take up to 10ms to com- |
read sequence. A stop condition can only be issued |
||
plete. Writes to undefined areas have no effect. The |
after the transmitting device has released the bus. See |
||
RWEL bit is reset by the completion of a nonvolatile |
Figure 4. |
||
write cycle, so the sequence must be repeated to |
|
||
again initiate another change to the CCR contents. |
Acknowledge |
||
If the sequence is not completed for any reason |
Acknowledge is a software convention used to indicate |
||
(by sending an incorrect number of bits or sending a |
|||
successful data transfer. The transmitting device, |
|||
start instead of a stop, for example) the RWEL bit is |
|||
either master or slave, will release the bus after trans- |
|||
not reset and the device remains in an active mode. |
|||
mitting eight bits. During the ninth clock cycle, the |
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|
||
– Writing all zeros to the status register resets both the |
receiver will pull the SDA line LOW to acknowledge |
||
WEL and RWEL bits. |
that it received the eight bits of data. Refer to Figure 5. |
||
– A read operation occurring between any of the previ- |
The device will respond with an acknowledge after rec- |
||
ous operations will not interrupt the register write |
ognition of a start condition and if the correct Device |
||
operation. |
|
Identifier and Select bits are contained in the Slave |
|
SERIAL COMMUNICATION |
Address Byte. If a write operation is selected, the |
||
device will respond with an acknowledge after the |
|||
Interface Conventions |
receipt of each subsequent eight bit word. The device |
||
will acknowledge all incoming data and address bytes, |
|||
The device supports a bidirectional bus oriented proto- |
except for: |
||
col. The protocol defines any device that sends data |
– The Slave Address Byte when the Device Identifier |
||
onto the bus as a transmitter, and the receiving device |
|||
and/or Select bits are incorrect |
|||
|
|
||
|
PRELIMINARY |
||
as the receiver. The device controlling the transfer is |
– All Data Bytes of a write when the WEL in the Write |
||
called the master and the device being controlled is |
|||
called the slave. The master always initiates data |
Protect Register is LOW |
||
transfers, and provides the clock for both transmit and |
– The 2nd Data Byte of a Status Register Write |
||
receive operations. Therefore, the devices in this fam- |
Operation (only 1 data byte is allowed) |
||
ily operate as slaves in all applications. |
|
REV 1.0.9 8/29/02 |
www.xicor.com |
Characteristics subject to change without notice. 7 of 22 |