XICOR X1205V8I, X1205V8, X1205S8I, X1205S8 Datasheet

Loading...
XICOR X1205V8I, X1205V8, X1205S8I, X1205S8 Datasheet

Preliminary Information

New Features

Repetitive Alarms &

Temperature Compensation

 

 

 

 

 

 

X1205

 

 

 

 

2-Wire RTC

 

 

Real Time Clock/Calendar

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FEATURES

 

 

 

 

 

 

• Modems

 

 

 

 

 

 

 

 

 

• Real Time Clock/Calendar

 

• Network Routers, Hubs, Switches, Bridges

 

• Cellular Infrastructure Equipment

—Tracks time in Hours, Minutes, and Seconds

• Fixed Broadband Wireless Equipment

—Day of the Week, Day, Month, and Year

 

 

• Pagers / PDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PRELIMINARY

 

 

 

 

 

• 2 Polled Alarms (Non-volatile)

 

• POS Equipment

 

 

 

 

 

 

 

—Settable on the Second, Minute, Hour, Day of

• Test Meters / Fixtures

 

 

 

 

 

the Week, Day, or Month

 

• Office Automation (Copiers, Fax)

—Repeat Mode (periodic interrupts)

 

• Home Appliances

 

 

 

 

 

 

 

• Oscillator Compensation on chip

 

• Computer Products

 

 

 

 

 

—Internal feedback resistor and compensation

• Other Industrial / Medical / Automotive

capacitors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

—64 position Digitally Controlled Trim Capacitor

DESCRIPTION

 

 

 

 

 

 

 

—6 digital frequency adjustment settings to

 

 

 

 

 

 

 

 

 

 

 

 

±30ppm

 

 

 

 

 

 

The X1205 device is a Real Time Clock with clock/

• Battery Switch or Super Cap Input

 

calendar, two polled alarms, oscillator compensation,

• 2-Wire™ Interface interoperable with I2C*

 

and battery backup switch.

 

 

 

 

 

—400kHz data transfer rate

 

The oscillator uses an external, low-cost 32.768kHz

• Low Power CMOS

 

 

 

 

 

 

crystal. All

compensation and

trim components are

—1.25µA Operating Current (Typical)

 

integrated on the chip. This eliminates several external

• Small Package Options

 

discrete components

and a trim capacitor, saving

—8-Lead SOIC and 8-Lead TSSOP

 

board area and component cost.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APPLICATIONS

 

 

 

 

 

 

The Real-Time Clock keeps track of time with separate

• Utility Meters

 

 

 

 

 

 

registers for Hours,

Minutes,

and Seconds. The

 

 

 

 

 

 

Calendar has separate registers for Date, Month, Year

• HVAC Equipment

 

 

 

 

 

 

 

 

 

 

 

 

and Day-of-week. The calendar is correct through

• Audio / Video Components

 

 

2099, with automatic leap year correction.

• Set Top Box / Television

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compensation

 

 

 

 

 

 

 

 

 

 

32.768kHz

X1

 

 

 

 

Oscillator

 

Frequency

1Hz

 

Timer

 

Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Calendar

 

 

 

 

 

 

 

 

 

 

 

 

Divider

 

 

 

 

 

 

X2

 

 

 

 

 

 

 

 

 

Logic

 

Keeping

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SRAM)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control

Control

Status

 

 

 

Registers

 

 

 

Registers

Alarm

 

 

Decode

 

 

(EEPROM)

(SRAM)

SCL

Serial

Logic

Mask

 

Interface

 

 

 

 

 

 

 

 

SDA

Decoder

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

Interrupt Enable

 

 

IRQ

 

 

 

 

 

 

 

 

Alarm

 

Compare

Alarm Regs

(EEPROM)

*I2C is a Trademark of Philips.

REV 1.0.9 8/29/02 www.xicor.com Characteristics subject to change without notice. 1 of 22

X1205 – Preliminary Information

DESCRIPTION (continued)

 

 

 

 

 

 

 

 

 

 

 

 

X1, X2

 

 

 

 

 

 

 

 

 

 

 

 

The powerful Dual Alarms can be set to any Clock/

The X1 and X2 pins are the input and output,

Calendar value for a match. For instance, every

respectively, of an inverting amplifier. An external

minute, every Tuesday, or 5:23 AM on March 21. The

32.768kHz quartz crystal is used with the X1205 to

alarms can be polled in the Status Register or provide

supply a timebase for the real time clock. The

a hardware interrupt

 

(IRQ

 

Pin).

There is

a repeat

recommended crystal is a Citizen CFS206-32.768KDZF.

mode for the alarms allowing a periodic interrupt.

 

Internal compensation circuitry is included to form a

The device offers a

backup power

input

pin. This

complete oscillator circuit. Care should be taken in the

placement of the crystal and the layout of the circuit.

VBACK pin allows the device to be backed up by battery

Plenty

of

ground

plane around the device and short

or SuperCap.

The

entire

X1205 device

 

 

is

fully

traces

to

X1 and

 

X2 are highly recommended. See

operational from 2.7 to 5.5 volts and the clock/calendar

 

Application section for more recommendations.

portion of the X1205 device remains fully operational

 

 

 

 

 

 

 

 

 

 

 

 

 

 

down to 1.8 volts (Standby Mode).

 

 

 

 

 

 

 

 

 

 

 

Figure 1. Recommended Crystal connection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTIONS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Pin

SOIC

 

 

X1205

8-Pin

 

TSSOP

 

 

 

 

 

 

 

 

 

 

 

 

 

X2

 

 

 

 

 

 

 

 

 

VBACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X1

 

1

 

8

 

VCC

 

1

8

 

 

 

 

SCL

POWER CONTROL OPERATION

 

 

 

 

 

 

 

 

X2

 

2

 

7

 

VBACK

VCC

 

2

7

 

 

 

 

SDA

The power control circuit accepts a VCC and a VBACK

 

IRQ

 

 

3

 

6

 

SCL

X1

 

3

6

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

4

 

5

 

SDA

X2

 

4

5

 

 

 

 

IRQ

 

input. The power control circuit powers the clock from

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VBACK when VCC < VBACK - 0.2V. It will switch back to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC = No internal connection

 

 

 

 

 

 

 

 

 

 

 

 

power the device from VCC when VCC exceeds VBACK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2. Power Control

Serial Clock (SCL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

The SCL input is used to clock all data into and out of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Voltage

 

 

 

 

 

 

 

 

 

 

 

 

the device. The input buffer on this pin is always active

 

VBACK

 

 

 

 

 

 

 

 

 

 

On

(not gated).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Off

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Data (SDA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA is a bidirectional pin used to transfer data into and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

out of the device. It has an open drain output and may

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

be wire ORed with other open drain or open collector

REAL TIME CLOCK OPERATION

outputs. The input buffer is always active (not gated).

The Real Time Clock (RTC) uses an external

An open drain output requires the use of a pull-up

32.768kHz quartz crystal to maintain an accurate inter-

resistor. The output circuitry controls the fall time of the

nal representation of second, minute, hour, day, date,

output signal with the use of a slope controlled pull-

month, and year. The RTC has leap-year correction.

down. The circuit is designed for 400kHz 2-wire inter-

The clock also corrects for months having fewer than

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

face speeds.

 

 

PRELIMINARY31 days and has a bit that controls 24 hour or AM/PM

VBACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

format. When the X1205 powers up after the loss of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

both VCC and VBACK, the clock will not operate until at

This input

provides a backup supply

 

voltage to

the

 

least one byte is written to the clock register.

device. VBACK supplies power to the device in the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

event the VCC supply fails. This pin can be connected

Reading the Real Time Clock

to a battery, a Supercap or tied to ground if not used.

The RTC is read by initiating a Read command and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt Output –

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

specifying the address corresponding to the register of

IRQ

 

 

 

 

 

 

 

 

 

 

 

 

This is an interrupt signal output. This signal notifies a

the Real Time Clock. The RTC Registers can then be

read in a Sequential Read Mode. Since the clock runs

host processor

that

an alarm

has

 

occurred

and

 

continuously and a read takes a finite amount of time,

requests action. It is an open drain active low output.

there is the possibility that the clock could change during

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REV 1.0.9 8/29/02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

www.xicor.com

 

 

Characteristics subject to change without notice. 2 of 22

X1205 – Preliminary Information

the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation.

Writing to the Real Time Clock

CCR access

The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a two step process (See section “Writing to the Clock/Control Registers.”)

The time and date may be set by writing to the RTC The CCR is divided into 5 sections. These are:

registers. To avoid changing the current time by an

 

 

ppm to –37 ppm whenPRELIMINARYusing a 12.5 pF load crystal.

uncompleted write operation, the current time value is

1. Alarm 0 (8 bytes; non-volatile)

loaded into a separate buffer at the falling edge of the

2. Alarm 1 (8 bytes; non-volatile)

clock on the ACK bit before the RTC data input bytes,

3. Control (4 bytes; non-volatile)

the clock continues to run. The new serial input data

4. Real Time Clock (8 bytes; volatile)

replaces the values in the buffer. This new RTC value

5. Status (1 byte; volatile)

is loaded back into the RTC Register by a stop bit at

Each register is read and written through buffers. The

the end of a valid write sequence. An invalid write

non-volatile portion (or the counter portion of the RTC) is

operation aborts the time update procedure and the

updated only if RWEL is set and only after a valid write

contents of the buffer are discarded. After a valid write

operation and stop bit. A sequential read or page write

operation the RTC will reflect the newly loaded data

operation provides access to the contents of only one

beginning with the next “one second clock cycle” after

section of the CCR per operation. Access to another sec-

the stop bit is written. The RTC continues to update

tion requires a new operation. Continued reads or writes,

the time while an RTC register write is in progress and

once reaching the end of a section, will wrap around to

the RTC continues to run during any nonvolatile write

the start of the section. A read or write can begin at any

sequences. A single byte may be written to the RTC

address in the CCR.

without affecting the other bytes.

 

 

 

 

It is not necessary to set the RWEL bit prior to writing

Accuracy of the Real Time Clock

 

 

 

 

 

 

the status register. Section 5 supports a single byte

The accuracy of the Real Time Clock depends on the

read or write only. Continued reads or writes from this

frequency of the quartz crystal that is used as the time

section terminates the operation.

base for the RTC. Since the resonant frequency of a

The state of the CCR can be read by performing a ran-

crystal is temperature dependent,

the

RTC perfor-

dom read at any address in the CCR at any time. This

mance will also be dependent upon temperature. The

returns

the contents of that register location. Addi-

frequency deviation of the crystal is a function of the

tional registers are read by performing a sequential

turnover temperature of the crystal from the crystal’s

read. The read instruction latches all Clock registers

nominal frequency. For example, a >20ppm frequency

into a

buffer, so an update of the clock does not

deviation translates into an accuracy of >1 minute per

change the time being read. A sequential read of the

month. These parameters are available from the

CCR will not result in the output of data from the mem-

crystal manufacturer. Xicor’s RTC family provides on-

ory array. At the end of a read, the master supplies a

chip crystal

compensation networks to

adjust

load-

stop condition to end the operation and free the bus.

capacitance

to tune oscillator

frequency from

+116

After a read of the CCR, the address remains at the

 

 

 

 

 

 

For more

detail information

see

the

Application

previous address +1 so the user can execute a current

address read of the CCR and continue reading the

section.

 

 

 

 

 

 

 

 

 

 

next Register.

 

 

 

 

 

 

CLOCK/CONTROL REGISTERS (CCR)

 

 

ALARM REGISTERS

The Control/Clock Registers are located in an area

There are two alarm registers whose contents mimic the

accessible following a slave byte of “1101111x” and

reads or writes to addresses [0000h:003Fh]. The

contents of the RTC register, but add enable bits and

clock/control memory map has memory addresses

exclude the 24 hour time selection bit. The enable bits

from 0000h to 003Fh. The defined addresses are

specify which registers to use in the comparison between

described in the Table 1. Writing to and reading from

the Alarm and Real Time Registers. For example:

the undefined addresses are not recommended.

 

 

 

 

 

 

 

 

 

REV 1.0.9 8/29/02

 

 

 

www.xicor.com

Characteristics subject to change without notice. 3 of 22

X1205 – Preliminary Information

– Setting the Enable Month Bit (EMOn*) bit in combi-

– The user can set the X1205 to alarm every Wednes-

nation with other enable bits and a specific alarm

 

day at 8:00 AM by setting the EDWn*, the EHRn*

time, the user can establish an alarm that triggers at

 

and EMNn* enable bits to ‘1’ and setting the DWAn*,

the same time once a year.

 

 

 

 

 

 

HRAn* and MNAn* Alarm registers to 8:00AM

 

*n = 0 for Alarm 0: N = 1 for Alarm 1

 

 

 

 

 

 

Wednesday.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– A daily alarm for 9:30PM results when the EHRn*

When there is a match, an alarm flag is set. The occur-

and EMNn* enable bits are set to ‘1’ and the HRAn*

rence of an alarm can be determined by polling the

and MNAn* registers are set to 9:30PM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AL0 and AL1 bits or by enabling the IRQ output, using

 

 

 

 

 

 

 

 

 

it as hardware flag.

 

 

 

 

 

 

 

 

*n = 0 for Alarm 0: N = 1 for Alarm 1

 

 

 

PRELIMINARY

 

 

 

 

 

 

 

 

 

 

 

The alarm enable bits are located in the MSB of the

 

 

 

 

 

 

 

 

particular register. When all enable bits are set to ‘0’,

 

 

 

 

 

 

 

 

there are no alarms.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 1. Clock/Control Memory Map

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

7

 

6

 

5

 

4

3

2

1

0

 

 

Default

Addr.

Type

 

Reg

 

 

 

 

 

 

 

 

 

Bit

 

 

 

Range

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

003F

Status

 

SR

BAT

 

 

AL1

AL0

 

0

 

0

RWEL

WEL

RTCF

 

 

01h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0037

RTC (SRAM)

 

Y2K

0

 

0

 

Y2K21

 

Y2K20

 

Y2K13

0

0

Y2K10

 

 

20h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0036

 

 

DW

0

 

0

 

0

 

0

 

0

DY2

DY1

DY0

0-6

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0035

 

 

YR

Y23

 

 

Y22

Y21

 

Y20

 

Y13

Y12

Y11

Y10

0-99

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0034

 

 

MO

0

 

0

 

0

 

G20

 

G13

G12

G11

G10

1-12

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0033

 

 

DT

0

 

0

 

D21

 

D20

 

D13

D12

D11

D10

1-31

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0032

 

 

HR

MIL

 

0

 

H21

 

H20

 

H13

H12

H11

H10

0-23

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0031

 

 

MN

0

 

 

M22

M21

 

M20

 

M13

M12

M11

M10

0-59

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0030

 

 

SC

0

 

 

S22

S21

 

S20

 

S13

S12

S11

S10

0-59

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0013

Control

 

DTR

0

 

0

 

0

 

0

 

0

DTR2

DTR1

DTR0

 

 

00h

 

(NONVOLATILE)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0012

 

ATR

0

 

0

 

ATR5

 

ATR4

 

ATR3

ATR2

ATR1

ATR0

 

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0011

 

 

INT

IM

 

 

AL1E

AL0E

 

0

 

0

X

X

X

 

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0010

 

 

0

0

 

0

 

0

 

0

 

0

0

0

0

 

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000F

Alarm1

 

Y2K1

0

 

0

 

A1Y2K21

 

A1Y2K20

 

A1Y2K13

0

0

A1Y2K10

 

 

20h

 

(NONVOLATILE)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000E

 

DWA1

EDW1

 

0

 

0

 

0

 

0

DY2

DY1

DY0

0-6

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000D

 

 

YRA1

 

 

 

 

Unused – Default = RTC Year value – Future expansion

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000C

 

 

MOA1

EMO1

 

0

 

0

 

A1G20

 

A1G13

A1G12

A1G11

A1G10

1-12

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000B

 

 

DTA1

EDT1

 

0

 

A1D21

 

A1D20

 

A1D13

A1D12

A1D11

A1D10

1-31

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000A

 

 

HRA1

EHR1

 

0

 

A1H21

 

A1H20

 

A1H13

A1H12

A1H11

A1H10

0-23

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0009

 

 

MNA1

EMN1

 

A1M22

A1M21

 

A1M20

 

A1M13

A1M12

A1M11

A1M10

0-59

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0008

 

 

SCA1

ESC1

 

A1S22

A1S21

 

A1S20

 

A1S13

A1S12

A1S11

A1S10

0-59

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0007

Alarm0

 

Y2K0

0

 

0

 

A0Y2K21

 

A0Y2K20

 

A0Y2K13

0

0

A0Y2K10

19/20

 

20h

 

(NONVOLATILE)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0006

 

DWA0

EDW0

 

0

 

0

 

0

 

0

DY2

DY1

DY0

0-6

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0005

 

 

YRA0

 

 

 

 

Unused – Default = RTC Year value – Future expansion

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0004

 

 

MOA0

EMO0

 

0

 

0

 

A0G20

 

A0G13

A0G12

A0G11

A0G10

1-12

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0003

 

 

DTA0

EDT0

 

0

 

A0D21

 

A0D20

 

A0D13

A0D12

A0D11

A0D10

1-31

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0002

 

 

HRA0

EHR0

 

0

 

A0H21

 

A0H20

 

A0H13

A0H12

A0H11

A0H10

0-23

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0001

 

 

MNA0

EMN0

 

A0M22

A0M21

 

A0M20

 

A0M13

A0M12

A0M11

A0M10

0-59

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0000

 

 

SCA0

ESC0

 

A0S22

A0S21

 

A0S20

 

A0S13

A0S12

A0S11

A0S10

0-59

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REV 1.0.9 8/29/02

 

 

 

 

 

 

www.xicor.com

Characteristics subject to change without notice.

4 of 22

X1205 – Preliminary Information

REAL TIME CLOCK REGISTERS

Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)

These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

Date of the Week Register (DW)

AL1, AL0: Alarm bits—Volatile

These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete.

Table 2. Status RegisterPRELIMINARY(SR) power to the device. The bit is set regardless of

This register provides a Day of the Week status and

uses three bits DY2 to DY0 to represent the seven

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW

days of the week. The counter advances in the cycle

0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical

(disabled) state. The RWEL bit must be set to “1” prior

value to a specific day of the week is arbitrary and may

to any writes to the Clock/Control Registers. Writes to

be decided by the system software designer. The

RWEL bit do not cause a nonvolatile write cycle, so the

default value is defined as ‘0’.

device is ready for the next operation immediately after

24 Hour Time

the stop condition. A write to the CCR requires both

the RWEL and WEL bits to be set in a specific

If the MIL bit of the HR register is 1, the RTC uses a

sequence.

24-hour format. If the MIL bit is 0, the RTC uses a 12-

WEL: Write Enable Latch—Volatile

hour format and H21 bit functions as an AM/PM indi-

cator with a ‘1’ representing PM. The clock defaults to

The WEL bit controls the access to the CCR and

standard time with H21=0.

memory array during a write operation. This bit is a

Leap Years

volatile latch that powers up in the LOW (disabled)

state. While the WEL bit is LOW, writes to the CCR or

Leap years add the day February 29 and are defined

any array address will be ignored (no acknowledge will

as those years that are divisible by 4. Years divisible by

be issued after the Data Byte). The WEL bit is set by

100 are not leap years, unless they are also divisible

writing a “1” to the WEL bit and zeroes to the other bits

by 400. This means that the year 2000 is a leap year,

of the Status Register. Once set, WEL remains set

the year 2100 is not. The X1205 does not correct for

until either reset to 0 (by writing a “0” to the WEL bit

the leap year in the year 2100.

and zeroes to the other bits of the Status Register) or

STATUS REGISTER (SR)

until the part powers up again. Writes to WEL bit do

not cause a nonvolatile write cycle, so the device is

The Status Register is located in the CCR memory

ready for the next operation immediately after the stop

condition.

map at address 003Fh. This is a volatile register only

 

and is used to control the WEL and RWEL write

RTCF: Real Time Clock Fail Bit—Volatile

enable latches, read two power status and two alarm

This bit is set to a ‘1’ after a total power failure. This is

bits. This register is separate from both the array and

the Clock/Control Registers (CCR).

a read only bit that is set by hardware (X1205 inter-

 

nally) when the device powers up after having lost all

Addr

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

003Fh

BAT

AL1

AL0

0

0

RWEL

WEL

RTCF

Default

0

0

0

0

0

0

0

1

BAT: Battery Supply—Volatile

whether VCC or VBACK is applied first. The loss of only one of the supplies does not result in setting the RTCF bit. The first valid write to the RTC after a complete power failure (writing one byte is sufficient) resets the RTCF bit to ‘0’.

This bit set to “1” indicates that the device is operating

from VBACK, not VCC. It is a read-only bit and is set/ reset by hardware (X1205 internally). Once the device

begins operating from VCC, the device sets this bit to “0”.

Unused Bits:

This device does not use bits 3 or 4 in the SR, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations.

REV 1.0.9 8/29/02

www.xicor.com

Characteristics subject to change without notice. 5 of 22

X1205 – Preliminary Information

INTERRUPT CONTROL REGISTER (INT)

 

 

DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm

Interrupt Control and Status Bits (IM, AL1E, AL0E)

 

adjustment and DTR0 gives 20 ppm adjustment.

 

 

 

 

 

 

There are two Interrupt Control bits, Alarm 1 Interrupt

 

A range from -30ppm to +30ppm can be represented

Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to

 

by using three bits above.

 

specifically enable or disable the alarm interrupt signal

 

Table 3. Digital Trimming Registers

output

 

 

. The interrupts are enabled when either the

 

(IRQ)

AL1E and AL0E bits are set to “1”, respectively.

 

 

 

 

 

 

 

 

 

DTR Register

 

Estimated frequency

 

 

 

 

 

 

 

 

 

 

 

 

Two volatile bits (AL1 and AL0), associated with the two

 

 

 

 

 

 

DTR2

DTR1

DTR0

 

PPM

alarms respectively, indicate if an alarm has happened.

 

 

 

 

 

 

 

0

0

0

 

0 (default)

These bits are set on an alarm condition regardless of

 

 

 

 

 

 

 

 

 

0

1

0

 

+10

 

 

 

 

 

 

 

 

 

 

 

 

whether the IRQ interrupt is enabled. The AL1 and AL0

 

 

 

 

 

 

bits in the status register are reset by the falling edge of

 

0

0

1

 

+20

the eighth clock of a read of the register containing the

 

 

 

 

 

 

 

0

1

1

 

+30

bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pulse Interrupt Mode

 

 

 

1

1

0

 

-10

The pulsed interrupt mode allows for repetitive

or

 

 

 

 

 

 

 

1

0

1

 

-20

recurring

alarm functionality. Hence an repetitive

or

 

 

 

 

 

 

 

1

1

1

 

-30

recurring alarm can be set for every nth second, or nth

 

 

 

 

 

 

 

 

 

 

 

 

 

 

minute, or nth hour, or nth date, or for the same day of

 

Analog Trimming Register (ATR) (Non-volatile)

the week. The pulsed interrupt mode can be consid-

 

 

 

 

 

 

 

ered a repetitive interrupt mode, with the repetition

 

Six analog trimming Bits from ATR5 to ATR0 are pro-

rate set by the time setting fo the alarm.

 

 

vided to adjust the on-chip loading capacitance range.

The Pulse Interrupt Mode is enabled when the IM bit is

 

The on-chip load capacitance ranges from 3.25pF to

 

18.75pF. Each bit has a different weight for capaci-

set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tance adjustment. In addition, using a Citizen CFS-206

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

crystal with different ATR bit combinations provides an

IM Bit

 

 

 

 

 

Interrupt / Alarm Frequency

 

 

 

 

 

 

 

 

estimated ppm range from +116ppm to -37ppm to the

 

 

 

 

 

 

 

 

 

 

 

0

 

 

Single Time Event Set By Alarm

 

 

nominal frequency compensation. The combination of

 

 

 

 

 

digital and analog trimming can give up to +146ppm

1

 

 

Repetitive / Recurring Time Event Set By Alarm

 

 

 

 

 

 

 

 

 

 

 

adjustment.

 

 

 

The Alarm

 

output will output a single pulse of

 

 

 

IRQ

 

The on-chip capacitance can be calculated as follows:

short duration (approximately 10-40ms) once the

 

 

 

 

 

 

 

alarm condition is met. If the interrupt mode bit (IM bit)

 

CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF

is set, then this pulse will be periodic.

 

 

Note that the ATR values are in two’s complement,

 

 

 

 

 

 

 

 

 

 

 

ON-CHIP OSCILLATOR COMPENSATION

 

 

with ATR(000000) = 11.0pF, so the entire range runs

 

 

 

 

 

 

 

 

 

 

 

from 3.25pF to 18.75pF in 0.25pF steps.

Digital Trimming Register (DTR) — DTR2, DTR1

 

 

The values calculated above are typical, and total load

and DTR0 (Non-Volatile)

 

 

 

 

capacitance seen by the crystal will include approxi-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PRELIMINARY

 

The digital trimming Bits DTR2, DTR1 and DTR0

 

mately 2pF of package and board capacitance in addi-

adjust the number of counts per second and average

 

tion to the ATR value.

 

the ppm error to achieve better accuracy.

 

 

See Application section and Xicor’s Application Note

 

 

 

 

 

 

 

 

 

 

 

DTR2 is a sign bit. DTR2=0 means frequency

 

AN154 for more information.

 

compensation is > 0. DTR2=1 means frequency

 

 

 

 

 

 

compensation is < 0.

 

 

 

 

 

 

 

 

REV 1.0.9 8/29/02

www.xicor.com

Characteristics subject to change without notice. 6 of 22

X1205 – Preliminary Information

WRITING TO THE CLOCK/CONTROL REGISTERS

Clock and Data

Changing any of the nonvolatile bits of the clock/con-

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

trol register requires the following steps:

reserved for indicating start and stop conditions. See

– Write a 02h to the Status Register to set the Write

Figure 3.

Enable Latch (WEL). This is a volatile operation, so

 

there is no delay after the write. (Operation pre-

Start Condition

ceeded by a start and ended with a stop).

All commands are preceded by the start condition,

– Write a 06h to the Status Register to set both the

which is a HIGH to LOW transition of SDA when SCL

Register Write Enable Latch (RWEL) and the WEL

is HIGH. The device continuously monitors the SDA

bit. This is also a volatile cycle. The zeros in the data

and SCL lines for the start condition and will not

byte are required. (Operation preceeded by a start

respond to any command until this condition has been

and ended with a stop).

met. See Figure 4.

– Write one to 8 bytes to the Clock/Control Registers

Stop Condition

with the desired clock, alarm, or control data. This

 

sequence starts with a start bit, requires a slave byte

All communications must be terminated by a stop

of “11011110” and an address within the CCR and is

condition, which is a LOW to HIGH transition of SDA

terminated by a stop bit. A write to the CCR changes

when SCL is HIGH. The stop condition is also used to

nonvolatile register values so these initiate a non-

place the device into the Standby power mode after a

volatile write cycle and will take up to 10ms to com-

read sequence. A stop condition can only be issued

plete. Writes to undefined areas have no effect. The

after the transmitting device has released the bus. See

RWEL bit is reset by the completion of a nonvolatile

Figure 4.

write cycle, so the sequence must be repeated to

 

again initiate another change to the CCR contents.

Acknowledge

If the sequence is not completed for any reason

Acknowledge is a software convention used to indicate

(by sending an incorrect number of bits or sending a

successful data transfer. The transmitting device,

start instead of a stop, for example) the RWEL bit is

either master or slave, will release the bus after trans-

not reset and the device remains in an active mode.

mitting eight bits. During the ninth clock cycle, the

 

 

– Writing all zeros to the status register resets both the

receiver will pull the SDA line LOW to acknowledge

WEL and RWEL bits.

that it received the eight bits of data. Refer to Figure 5.

– A read operation occurring between any of the previ-

The device will respond with an acknowledge after rec-

ous operations will not interrupt the register write

ognition of a start condition and if the correct Device

operation.

 

Identifier and Select bits are contained in the Slave

SERIAL COMMUNICATION

Address Byte. If a write operation is selected, the

device will respond with an acknowledge after the

Interface Conventions

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

The device supports a bidirectional bus oriented proto-

except for:

col. The protocol defines any device that sends data

– The Slave Address Byte when the Device Identifier

onto the bus as a transmitter, and the receiving device

and/or Select bits are incorrect

 

 

 

PRELIMINARY

as the receiver. The device controlling the transfer is

– All Data Bytes of a write when the WEL in the Write

called the master and the device being controlled is

called the slave. The master always initiates data

Protect Register is LOW

transfers, and provides the clock for both transmit and

– The 2nd Data Byte of a Status Register Write

receive operations. Therefore, the devices in this fam-

Operation (only 1 data byte is allowed)

ily operate as slaves in all applications.

 

REV 1.0.9 8/29/02

www.xicor.com

Characteristics subject to change without notice. 7 of 22

+ 15 hidden pages