White Electronic Designs EDI9LC644V2012BC, EDI9LC644V2010BC, EDI9LC644V1612BC, EDI9LC644V1610BC, EDI9LC644V1510BC Datasheet

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EDI9LC644V

128Kx32 SSRAM/1Mx32 SDRAM

EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP

FEATURES

DESCRIPTION

νClock speeds:

SSRAM: 200, 166,150, and 133 MHz

SDRAMs: 125 and 100 MHz

νDSP Memory Solution

Texas Instruments TMS320C6201

Texas Instruments TMS320C6701

νPackaging:

153 pin BGA, JEDEC MO-163

ν3.3V Operating supply voltage

νDirect control interface to both the SSRAM and SDRAM ports on the “C6x”

νCommon address and databus

ν65% space savings vs. monolithic solution

νReduced system inductance and capacitance

The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 1Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 1Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA.

The EDI9LC644VxxBC provides a total memory solution for the Texas Instr uments TMS320C6201 and the TMS320C6701 DSPs

The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port .

The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port .

FIG. 1

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BOTTOM VIEW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTION

 

 

1

2

3

4

 

 

 

 

 

 

5

 

 

 

 

 

6

7

8

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0-16

Address Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

DQ19

DQ23

VCC

 

 

 

VSS

 

 

 

 

VSS

VSS

VCC

DQ24

DQ28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

DQ0-31

Data Bus

 

 

 

DQ18

DQ22

VCC

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

VSS

VCC

DQ25

DQ29

 

 

 

 

B

 

 

 

 

 

 

 

SDCE

 

 

 

B

 

 

 

 

SSCLK

SSRAM Clock

 

 

 

VCCQ

VCCQ

VCC

 

 

 

 

 

 

 

 

 

SDA10

NC

VCC

VCCQ

VCCQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

SDWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSRAM Address Status Control

 

 

 

 

 

 

 

 

 

C

SSADC

 

 

D

DQ17

DQ21

VCC

 

 

 

VSS

 

 

 

 

VSS

VSS

VCC

DQ26

DQ30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSRAM Write Enable

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

SSWE

 

 

 

 

DQ16

DQ20

VCC

 

 

 

VSS

SDCLK

VSS

VCC

DQ27

DQ31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSRAM Output Enable

 

 

E

 

 

 

E

 

 

 

 

SSOE

 

 

F

VCCQ

VCCQ

VCC

 

 

 

VSS

 

 

 

 

VSS

VSS

VCC

VCCQ

VCCQ

F

 

 

 

 

SDCLK

SDRAM Clock

 

 

 

NC

NC

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

A2

A4

A5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM Row Address Strobe

 

 

G

 

SDRAS

 

 

 

SDCAS

 

G

 

 

 

SDRAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM Column Address Strobe

 

 

H

NC

NC

A8

 

 

 

VSS

 

 

 

 

VSS

NC

A1

A3

A10

H

SDCAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM Write Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J

A6

A7

A9

 

 

 

VSS

 

 

 

 

VSS

NC

A0

A11

A12

J

 

 

 

 

SDWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA10

SDRAM Address 10/auto precharge

 

 

K

NC/A17

NC/A18

NC/A19

 

 

 

VSS

 

 

 

 

VSS

NC

NC

A13

A14

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0-3

SSRAM Byte Write Enables

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BWE

 

 

L

NC

NC

NC

 

BWE2

 

 

BWE3

NC

NC

A15

A16

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM SDQM 0 - 3

 

 

 

VCCQ

VCCQ

VCC

 

 

 

 

0

 

 

 

 

 

1

NC

VCC

VCCQ

VCCQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

 

 

BWE

 

 

 

BWE

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSCE

Chip Enable SSRAM Device

 

 

N

DQ12

DQ11

VCC

 

 

 

VSS

 

 

 

 

VSS

VSS

VCC

DQ4

DQ0

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDCE

Chip Enable SDRAM Device

 

 

P

DQ13

DQ10

VCC

 

 

 

VSS

 

SSCLK

VSS

VCC

DQ5

DQ1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

VCC

Power Supply pins, 3.3V

 

 

R

VCCQ

VCCQ

VCC

 

 

 

VSS

 

 

 

 

VSS

VSS

VCC

VCCQ

VCCQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

VCCQ

Data Bus Power Supply pins,

 

 

 

DQ14

DQ9

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

VCC

DQ6

DQ2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V (2.5V future)

 

 

T

SSADC

 

SSWE

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

Ground

 

 

 

DQ15

DQ8

VCC

 

 

 

 

 

 

 

 

 

 

 

 

NC

VCC

DQ7

DQ3

 

 

 

 

 

 

 

 

 

U

 

SSOE

 

 

 

 

SSCE

 

 

 

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

No Connect

 

 

 

1

2

3

4

 

 

 

 

 

 

5

 

 

 

 

 

6

7

8

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

January 2002 Rev. 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

ECO# 14667

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EDI9LC644V

FIG. 2 BLOCK DIAGRAM

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EDI9LC644V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT FUNCTIONAL DESCRIPTIONS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Type

Signal

Polarity

 

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSCLK

Input

Pulse

Positive Edge

The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.

 

 

 

 

 

 

 

 

When sampled at the positive rising edge of the clock,

 

 

 

and

 

define the operation

 

SSADS

 

 

 

 

 

SSADS,

SSOE,

SSWE

 

 

SSOE

 

 

Input

Pulse

Active Low

to be executed by the SSRAM.

 

 

SSWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Pulse

Active Low

 

 

disable or enable SSRAM device operation.

 

 

 

SSCE

SSCE

 

 

SDCLK

Input

Pulse

Positive Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

 

 

 

SDCE

Input

Pulse

Active Low

SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.

 

 

 

 

 

 

 

 

 

 

 

 

When sampled at the positive rising edge of the clock,

 

 

 

 

 

 

 

define the

 

 

SDRAS

 

 

 

 

 

SDCAS,

 

SDRAS,

and

SDWE

 

 

SDCAS

 

Input

Pulse

Active Low

operation to be executed by the SDRAM.

 

 

SDWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address bus for SSRAM and SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

A0 and A1 are the burst address inputs for the SSRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled

 

 

 

 

 

 

 

 

 

 

 

 

 

at the rising clock edge.

 

 

 

A0-16,

Input

Level

During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at

 

 

SDA10

 

 

 

the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge

 

 

 

 

 

 

 

 

 

 

 

 

 

operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and

 

 

 

 

 

 

 

 

 

 

 

 

 

A11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low,

 

 

 

 

 

 

 

 

 

 

 

 

 

autoprecharge is disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

During a Precharge command cycle, SDA10 is used in conjunction with A11 to control which bank(s)

 

 

 

 

 

 

 

 

 

 

 

 

 

to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of

 

 

 

 

 

 

 

 

 

 

 

 

 

A11. If SDA10 is low, then A11 is used to define which bank to precharge.

 

 

DQ0-31

Input

Level

Data Input/Output are multiplexed on the same pins.

 

 

 

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BWE0-3

Input

Pulse

 

BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM.

 

 

 

 

 

 

 

 

 

 

 

 

 

BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.

VCC, VSS

Supply

 

 

Power and ground for the input buffers and the core logic.

 

 

 

VCCQ

Supply

 

 

Data base power supply pins, 3.3V (2.5V future).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

ABSOLUTE MAXIMUM RATINGS

Voltage on Vcc Relative to Vss

-0.5V to +4.6V

Vin (DQx)

-0.5V to Vcc +0.5V

Storage Temperature (BGA)

-55°C to +125°C

Junction Temperature

+175°C

Short Circuit Output Current

100 mA

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

EDI9LC644V

RECOMMENDED DC OPERATING

CONDITIONS

(0°C - TA - 70°C;

VCC = 3.3V -5% / +10% UNLESS OTHERWISE NOTED)

Parameter

Symbol

Min

Max

Units

 

 

 

 

 

Supply Voltage1

VCC

3.135

3.6

V

Input High Voltage1,2

VIH

2.0

VCC +0.3

V

Input Low Voltage1,2

VIL

-0.3

0.8

V

Input Leakage Current

ILI

-10

10

µA

0 - VIN - Vcc

 

 

 

 

Output Leakage (Output Disabled)

ILO

-10

10

µA

0 - VIN - Vcc

 

 

 

 

Output High (IOH = -4mA)1

VOH

2.4

V

Output Low (IOL = 8mA)1

VOL

0.4

V

NOTES:

1.All voltages referenced to Vss (GND).

2.Overshoot: VIH £ +6.0V for t - tKC/2 Underershoot: VIL ³ -2.0V for t - tKC/2

DC ELECTRICAL CHARACTERISTICS

Description

 

 

 

 

 

 

Conditions

Symbol

Frequency

Typ

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply Current:

 

 

 

 

 

 

 

 

 

 

133MHz

400

550

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating (1,2,3)

 

SSRAM Active / DRAM Auto Refresh

ICC1

150MHz

450

580

mA

 

 

 

 

 

 

 

 

 

 

 

166MHz

500

625

 

 

 

 

 

 

 

 

 

 

 

 

200MHz

TBD

TBD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply Current

 

 

 

 

 

 

 

 

 

 

133MHz

300

450

 

Operating1,2,3

 

SSRAM Active / DRAM Idle

ICC2

150MHz

350

480

mA

 

 

 

 

 

 

 

 

 

 

 

166MHz

400

525

 

 

 

 

 

 

 

 

 

 

 

 

200MHz

TBD

TBD

 

Power Supply Current

 

 

 

 

 

 

 

 

 

 

83MHz

220

240

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating1,2,3

 

SDRAM Active / SSRAM Idle

ICC3

100MHz

235

250

mA

 

 

 

 

 

 

 

 

 

 

 

125MHz

255

280

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and

 

 

£ VCC -0.2V,

ISB1

 

20.0

40.0

 

 

SSCE

SDCE

 

 

CMOS Standby

 

All other inputs at VSS +0.2 £ VIN or

 

 

 

 

mA

 

 

VIN £ VCC -0.2V, Clk frequency = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and

 

£ VIH min

ISB2

 

30.0

55.0

 

 

 

SSCE

SDCE

 

 

TTL Standby

 

All other inputs at VIL max £ VIN or

 

 

 

 

mA

 

 

VIN £ VCC -0.2V, Clk frequency = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto Refresh

 

 

 

 

 

 

 

 

 

ICC5

 

190

250

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

1.ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.

2.“Device idle” means device is deselected (CE ³ VIH) Clock is running at max frequency and Addresses are switching each cycle.

3.Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.

BGA CAPACITANCE

Description

Conditions

Symbol

Typ

Max

Units

Address Input Capacitance1

TA = 25°C; f = 1MHz

CI

5

8

pF

Input/Output Capacitance (DQ)1

TA = 25°C; f = 1MHz

CO

8

10

pF

Control Input Capacitance1

TA = 25°C; f = 1MHz

CA

5

8

pF

Clock Input Capacitance1

TA = 25°C; f = 1MHz

CCK

4

6

pF

NOTE:

1. This parameter is sampled.

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

4

EDI9LC644V

SSRAM AC CHARACTERISTICS (EDI9LC644V)

 

Symbol

 

200MHz

 

 

166MHz

 

 

150MHz

 

 

133MHz

 

 

Parameter

 

Min

Max

Min

Max

Min

Max

Min

Max

Units

Clock Cycle Time

tKHKH

5

 

 

 

6

 

 

 

7

 

 

 

8

 

 

 

ns

Clock HIGH Time

tKLKH

1.6

 

 

2.4

 

 

2.6

 

 

2.8

 

 

ns

Clock LOW Time

tKHKL

1.6

 

 

2.4

 

 

2.6

 

 

2.8

 

 

ns

Clock to output valid

tKHQV

 

 

2.5

 

 

3.5

 

 

3.8

 

 

4.0

ns

Clock to output invalid

tKHQX

1.5

 

 

1.5

 

 

1.5

 

 

1.5

 

 

ns

Clock to output on Low-Z

tKQLZ

0

 

 

 

0

 

 

 

0

 

 

 

0

 

 

 

ns

Clock to output in High-Z

tKQHZ

1.5

3

1.5

3.5

1.5

3.8

1.5

4.0

ns

Output Enable to output valid

tOELQV

 

 

2.5

 

 

3.5

 

 

3.8

 

 

4.0

ns

Output Enable to output in Low-Z

tOELZ

0

 

 

 

0

 

 

 

0

 

 

 

0

 

 

 

ns

Output Enable to output in High-Z

tOEHZ

 

 

3.0

 

 

3.5

 

 

3.5

 

 

3.8

ns

Address, Control, Data-in Setup Time to Clock

tS

1.5

 

 

1.5

 

 

1.5

 

 

1.5

 

 

ns

Address, Control, Data-in Hold Time to Clock

tH

0.5

 

 

0.5

 

 

0.5

 

 

0.5

 

 

ns

SSRAM OPERATION TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Address Used

 

SSCE

 

 

SSADS

 

SSWE

 

SSOE

DQ

Deselected Cycle, Power Down

None

 

H

 

L

 

X

 

X

High-Z

WRITE Cycle, Begin Burst

External

 

L

 

L

 

L

 

X

D

READ Cycle, Begin Burst

External

 

L

 

L

 

H

 

L

Q

READ Cycle, Begin Burst

External

 

L

 

L

 

H

 

H

High-Z

READ Cycle, Suspend Burst

Current

 

X

 

H

 

H

 

L

Q

READ Cycle, Suspend Burst

Current

 

X

 

H

 

H

 

H

High-Z

READ Cycle, Suspend Burst

Current

 

H

 

H

 

H

 

L

Q

READ Cycle, Suspend Burst

Current

 

H

 

H

 

H

 

H

High-Z

WRITE Cycle, Suspend Burst

Current

 

X

 

H

 

L

 

X

D

WRITE Cycle, Suspend Burst

Current

 

H

 

H

 

L

 

X

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

1.X means “don’t care”, H means logic HIGH. L means logic LOW.

2.All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.

3.Suspending burst generates wait cycle

4.For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time.

5.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

SSRAM PARTIAL TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

 

SSWE

 

BWE0

 

BWE1

 

BWE2

 

BWE3

READ

 

H

 

X

 

X

 

X

 

X

WRITE one Byte (DQ0-7)

 

L

 

L

 

H

 

H

 

H

WRITE all Bytes

 

L

 

L

 

L

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs EDI9LC644V2012BC, EDI9LC644V2010BC, EDI9LC644V1612BC, EDI9LC644V1610BC, EDI9LC644V1510BC Datasheet

EDI9LC644V

FIG. 3 SSRAM READ TIMING

FIG. 4 SSRAM WRITE TIMING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

6

 

 

 

 

EDI9LC644V

SDRAM AC CHARACTERISTICS

 

 

 

 

 

 

Symbol

 

125MHz

 

 

100MHz

 

 

83MHz

 

 

Parameter

 

 

Min

Max

Min

 

 

Max

Min

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Cycle Time1

CL = 3

tCC

8

 

1000

10

 

1000

12

 

1000

ns

 

 

 

 

 

CL = 2

tCC

10

 

1000

12

 

1000

15

 

1000

 

Clock to valid Output delay1,2

 

tSAC

 

 

6

 

 

7

 

 

8

ns

Output Data Hold Time2

 

tOH

3

 

 

 

3

 

 

 

3

 

 

 

ns

Clock HIGH Pulse Width3

 

tCH

3

 

 

 

3

 

 

 

3

 

 

 

ns

Clock LOW Pulse Width3

 

tCL

3

 

 

 

3

 

 

 

3

 

 

 

ns

Input Setup Time3

 

tSS

2

 

 

 

2

 

 

 

2

 

 

 

ns

Input Hold Time3

 

tSH

1

 

 

 

1

 

 

 

1

 

 

 

ns

CLK to Output Low-Z2

 

tSLZ

2

 

 

 

2

 

 

 

2

 

 

 

ns

CLK to Output High-Z

 

tSHZ

 

 

7

 

 

7

 

 

8

ns

Row Active to Row Active Delay4

 

tRRD

20

 

 

 

20

 

 

 

24

 

 

 

ns

 

 

to

 

Delay4

 

tRCD

20

 

 

 

20

 

 

 

24

 

 

 

ns

 

RAS

CAS

 

 

 

 

 

 

 

 

 

 

Row Precharge Time4

 

tRP

20

 

 

 

20

 

 

 

24

 

 

 

ns

Row Active Time4

 

tRAS

50

 

10,000

50

 

10,000

60

 

10,000

ns

Row Cycle Time - Operation4

 

tRC

70

 

 

 

80

 

 

 

90

 

 

 

ns

Row Cycle Time - Auto Refresh4,8

 

tRFC

70

 

 

 

80

 

 

 

90

 

 

 

ns

Last Data in to New Column Address Delay5

tCDL

1

 

 

 

1

 

 

 

1

 

 

 

CLK

Last Data in to Row Precharge5

 

tRDL

1

 

 

 

1

 

 

 

1

 

 

 

CLK

Last Data in to Burst Stop5

 

tBDL

1

 

 

 

1

 

 

 

1

 

 

 

CLK

Column Address to Column Address Delay6

tCCD

1.5

 

 

 

1.5

 

 

 

1.5

 

 

CLK

Number of Valid Output Data7

 

 

2

 

 

 

2

 

 

 

2

 

 

 

ea

 

 

 

 

 

 

 

1

 

 

 

2

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

1.Parameters depend on programmed CAS latency.

2.If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.

3.Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.

4.The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.

5.Minimum delay is required to complete write.

6.All devices allow every cycle column address changes.

7.In case of row precharge interrupt, auto precharge and read burst stop.

8.A new command may be given tRFC after self-refresh exit.

7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI9LC644V

CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM

(UNIT = NUMBER OF CLOCK)

Frequency

CAS

tRC

tRAS

tRP

tRRD

tRCD

tCCD

tCDL

tRDL

 

Latency

70ns

50ns

20ns

20ns

20ns

10ns

10ns

10ns

125MHz (8.0ns)

3

9

6

3

2

3

1

1

1

100MHz (10.0ns)

3

7

5

2

2

2

1

1

1

83MHz (12.0ns)

2

6

4

2

2

2

1

1

1

 

 

 

 

 

 

 

 

 

 

CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM

(UNIT = NUMBER OF CLOCK)

Frequency

CAS

tRC

tRAS

tRP

tRRD

tRCD

tCCD

tCDL

tRDL

 

Latency

70ns

50ns

20ns

20ns

20ns

10ns

10ns

10ns

100MHz (12.0ns)

3

7

5

2

2

2

1

1

1

83MHz (12.0ns)

2

6

5

2

2

2

1

1

1

 

 

 

 

 

 

 

 

 

 

REFRESH CYCLE PARAMETERS

 

 

 

-10

 

 

-12

 

 

Parameter

Symbol

Min

 

 

Max

Min

 

 

Max

Units

 

 

 

 

 

 

 

 

 

Refresh Period1,2

tREF

 

64

 

64

ms

NOTES:

1.4096 cycles

2.Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device.

SDRAM COMMAND TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA10

Notes

Function

 

SDCE

SDRAS

 

SDCAS

SDWE

BWE

A11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A9-0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode Register Set

 

L

 

L

 

L

 

L

X

OP CODE

 

Auto Refresh (CBR)

 

L

 

L

 

L

 

H

X

X

X

 

Precharge

Single Bank

 

L

 

L

 

H

 

L

X

BA

L

2

 

Precharge all Banks

 

L

 

L

 

H

 

L

X

X

H

 

Bank Activate

 

 

L

 

L

 

H

 

H

X

BA

Row Address

2

Write

 

 

L

 

H

 

L

 

L

X

BA

L

2

Write with Auto Precharge

 

L

 

H

 

L

 

L

X

BA

H

2

Read

 

 

L

 

H

 

L

 

L

X

BA

L

2

Read with Auto Precharge

 

L

 

H

 

L

 

H

X

BA

H

2

Burst Termination

 

 

L

 

H

 

H

 

L

X

X

X

3

No Operation

 

 

L

 

H

 

H

 

H

X

X

X

 

Device Deselect

 

 

H

 

X

 

X

 

X

X

X

X

 

Data Write/Output Disable

 

X

 

X

 

X

 

X

L

X

X

4

Data Mask/Output Disable

 

X

 

X

 

X

 

X

H

X

X

4

NOTES:

1. All of the SDRAM operations are defined by states of SDCE, SDWE, SDRAS, SDCAS, and BWE0-3 at the positive rising edge of the clock.

2.Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected.

3.During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.

4.The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

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