White Electronic Designs EDI8L32512V15AI, EDI8L32512V15AC, EDI8L32512V12AC, EDI8L32512V20AI, EDI8L32512V20AC Datasheet

EDI8L32512V

512Kx32 SRAM MODULE, 3.3V

	FEATURES	The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The
	■ DSP Memory Solution	device is available with access times of 12, 15, 17 and 20ns
		allowing the creation of a no wait state DSP and RISC micropro-
	NOT
	• ADSP-21060L (SHARC)	cessor memory solutions.
	• ADSP-21062L (SHARC)
		The device can be configured as a 512K x 32 and used to create a
	•Texas Instruments TMS320LC31
		single chip external data memory solution for TI’s TMS320LC31
	■ RISC Memory Solution
		(figure 5), or Analog’s SHARC™ DSP (figure 6).
	• MPC860 (Power Quic)	The device provides a 56% space savings when compared to four
	■ Random Access Memory Array	512K x 8, 36 pin SOJs. In addition the EDI8L32512C has only a 10pF
	• Fast Access Times: 12, 15, 17, and 20ns	load on the data lines vs. 32pf for four plastic SOJs.
	• Individual Byte Enables	The device provides a memory upgrade of the EDI8L32256V (256K
	• User configurable organization with Minimal Additional Logic	x 32) or the EDI8L32128V (128K x 32) (figure 8). Alternatively, the
		device’s chip enables can configure it as a 1M x 16. A 1Mx 48
	• Master Output Enable and Write Control
		program memory array for Analog’s SHARC DSP is created using
	• TTL Compatible Inputs and Outputs
		three devices (figure 7). If this memory is too deep, two 512K x 24s
	• Fully Static, No Clocks
		(EDI8L24512V) can be used to create a 512K x 48 array or two 128K
	■ Surface Mount Package	x 24s (EDI8L24128V) can be used to create a 128K x 48 array.
	• 68 Lead PLCC, No. 99 JEDEC M0-47AE	Note: Solder Reflow Temperature should not exceed 260° C for 10 seconds.
	• Small Footprint, 0.990 Sq. In.
	RECOMMENDED

• Multiple Ground Pins for Maximum Noise Immunity

■ Single +3.3V (± 5%) Supply Operation

FIG. 1 PIN CONFIGURATION

TOP VIEW

						DQ16			A18					A17																	E0 NC						VCC				NC NC																A16				A15				A14				DQ15
																			E3				E2				E1																						G				W
	9 8												7						6 5							4				3 2						1				68 67								66				65 64								63				62 61
DQ17	10																																																																									60	DQ14
																																																																										59	DQ13
DQ18	11
																																																																										58	DQ12
DQ19	12
																																																																										57	VSS
VSS	13
																																																																										56	DQ11
DQ20	14
																																																																										55	DQ10
DQ21	15
																																																																										54	DQ9
DQ22	16
																																																																										53	DQ8
DQ23	17
																																																																										52	VCC
VCC	18																																																																									51	DQ7
DQ24	19
																																																																										50	DQ6
DQ25	20
																																																																										49	DQ5
DQ26	21
																																																																										48	DQ4
DQ27	22
																																																																										47	VSS
VSS	23
																																																																										46	DQ3
DQ28	24
																																																																										45	DQ2
DQ29	25
																																																																										44	DQ1
DQ30	26
	27						28		29							30			31						32				33			34				35				36				37				38				39				40				41				42				43
				DQ31				A6					A5				A4 A3									A2				A1			A0				VCC				A13				A12				A11				A10				A9				A8				A7			DQ0

NOTE: For memory upgrade information, refer to Page 7, Figure 8 “EDI MCM-L upgrade path.

October 2000 Rev. 3

ECO# 13316

FOR

PIN DESCRIPTION

A0-18

Address Inputs

0-3

Chip Enables

E

(One per Byte)

Master Write Enable

NEW

W

G

Master Output

Enable

DQ0-31

Common Data

Input/Output

VCC

Power (+3.3V± 5%)

VSS

Ground

NC

No Connection

E0

DESIGN

BLOCK DIAGRAM

A0-18

19

G

W

512K x 32

DQ0-DQ7

Memory

DQ8-DQ15

E1

Array

DQ16-DQ23

E2

DQ24-DQ31

1

E3

White Electronic Designs Corporation • [phone] • www.whiteedc.com

EDI8L32512V

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Voltage on any pin relative to VSS	-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial	0° C to +70° C
Industrial	-40° C to +85° C
Storage Temperature, Plastic	-55° C to +125° C
Power Dissipation	2.5 Watts
Output Current	20 mA
Junction Temperature, TJ	+175° C

* Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TRUTH TABLE

	E			W			G		Mode	Output	Power
	H			X			X		Standby	High Z	Icc2, Icc3
	L			H			H		Output Deselect	High Z	Icc1
	L			H			L		Read	Data Out	Icc1
	L			L			X		Write	Data In	Icc1

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	3.135	3.3	3.465	V
Supply Voltage	VSS	0	0	0	V
Input High Voltage	VIH	2.2	—	Vcc +0.3	V
Input Low Voltage	VIL	-0.3	—	+0.8	V

CAPACITANCE

(f = 1.0MHz, VIN = VCC or VSS)

Parameter		Sym				Max	Unit
Address Lines		CI				30	pF
Data Lines		CD/Q				10	pF
Write & Output Enable Line						30	pF
		W,		G
Chip Enable Line		E0-3				8	pF

DC ELECTRICAL CHARACTERISTICS

(VCC = 3.3V, TA = 25˚C)

Parameter	Symbol								Conditions		12 & 15			17 & 20		Units
										Min	Typ	Max	Min	Typ	Max
Operating Power Supply Current	ICC1			W				= VIL, II/O = 0mA, Min Cycle		—	440	720	—	440	640	mA
Standby (TTL) Power Supply Current	ICC2						≥		VIH, VIN ≤ VIL or VIN ≥ VIH	—	100	200	—	100	200	mA
					E
Full Standby Power CMOS	ICC3					≥			VCC -0.2V
			E							—	60	100	—	60	100	mA
Supply Current		VIN ≥ VCC -0.2V or VIN ≤ 0.2V
Input Leakage Current	ILI	VIN = 0V to VCC								—	—	± 10	—	—	± 10	A
Output Leakage Current	ILO	VI/O = 0V to VCC								—	—	± 10	—	—	± 10	A
Output High Voltage	VOH	IOH = -4.0mA								2.4	—	—	2.4	—	—	V
Output Low Voltage	VOL	IOL = 4.0mA								—	—	0.4	—	—	0.4	V

AC TEST CONDITIONS

Figure 1	Vcc	Figure 2	Vcc
	480Ω		480Ω
Q		Q
255Ω	30pF	255Ω	5pF

Input Pulse Levels	VSS to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Levels	1.5V
Output Load	Figure 1

(NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF, Figure 2)

White Electronic Designs Corporation • [phone] • www.whiteedc.com

2

EDI8L32512V

AC CHARACTERISTICS – READ CYCLE

(VCC = 3.3V, Vss = 0V, TA = 0˚C to + 70˚C )

	Symbol		12ns			15ns				17ns			20ns
Parameter	JEDEC	Alt.	Min		Max	Min		Max	Min		Max	Min		Max	Units
Read Cycle Time	tAVAV	tRC	12			15			17			20			ns
Address Access Time	tAVQV	tAA			12			15			17			20	ns
Chip Enable Access Time	tELQV	tACS			10			12			15			20	ns
Chip Enable to Output in Low Z (1)	tELQX	tCLZ	3			3			3			3			ns
Chip Disable to Output in High Z (1)	tEHQZ	tCHZ			6			7			8			9	ns
Output Hold from Address Change	tAVQX	tOH	3			3			3			3			ns
Output Enable to Output Valid	tGLQV	tOE			6			7			8			9	ns
Output Enable to Output in Low Z (1)	tGLQX	tOLZ	3			3			3			3			ns
Output Disable to Output in High Z (1)	tGHQZ	tOHZ			6			7			8			9	ns

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS – WRITE CYCLE

(VCC = 3.3V, Vss = 0V, TA = 0˚C to + 70˚C )

	Symbol			12ns			15ns			17ns			20ns
Parameter	JEDEC	Alt.	Min		Max	Min		Max	Min		Max	Min		Max	Units
Write Cycle Time	tAVAV	tWC	12			15			17			20			ns
Chip Enable to End of Write	tELWH	tCW	8			10			11			12			ns
	tELEH	tCW	8			10			11			12			ns
Address Setup Time	tAVWL	tAS	0			0			0			0			ns
	tAVEL	tAS	0			0			0			0			ns
Address Valid to End of Write	tAVWH	tAW	8			10			11			12			ns
	tAVEH	tAW	8			10			11			12			ns
Write Pulse Width	tWLWH	tWP	8			10			11			12			ns
	tELEH	tWP	8			10			11			12			ns
Write Recovery Time	tWHAX	tWR	0			0			0			0			ns
	tEHAX	tWR	0			0			0			0			ns
Data Hold Time	tWHDX	tDH	0			0			0			0			ns
	tEHDX	tDH	0			0			0			0			ns
Write to Output in High Z (1)	tWLQZ	tWHZ	0		6	0		7	0		8	0		9	ns
Data to Write Time	tDVWH	tDW	6			7			8			9			ns
	tDVEH	tDW	6			7			8			9			ns
Output Active from End of Write (1)	tWHQX	tWLZ	3			3			3			3			ns

1. This parameter is guaranteed by design but not tested.

3	White Electronic Designs Corporation • [phone] • www.whiteedc.com