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SST/U5545NL Series |
New Product |
Vishay Siliconix |
Monolithic N-Channel JFET Duals
PRODUCT SUMMARY |
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Part Number |
VGS(off) (V) |
V(BR)GSS Min (V) |
gfs Min (mS) |
IG Max (pA) |
jVGS1 - VGS2j Max (mV) |
U5545NL |
-0.5 to -4.5 |
-50 |
1.5 |
-50 |
5 |
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SST/U5546NL |
-0.5 to -4.5 |
-50 |
1.5 |
-50 |
10 |
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SST/U5547NL |
-0.5 to -4.5 |
-50 |
1.5 |
-50 |
15 |
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FEATURES |
BENEFITS |
APPLICATIONS |
D Anti Latchup Capability |
D External Substrate Bias—Avoids Latchup |
D Wideband Differential Amps |
D Monolithic Design |
D Tight Differential Match vs. Current |
D High-Speed, Temp-Compensated, |
D High Slew Rate |
D Improved Op Amp Speed, Settling Time |
Single-Ended Input Amps |
D Low Offset/Drift Voltage |
Accuracy |
D High-Speed Comparators |
D Low Gate Leakage: 3 pA |
D Minimum Input Error/Trimming Requirement |
D Impedance Converters |
D Low Noise |
D Insignificant Signal Loss/Error Voltage |
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D High CMRR: 100 dB |
D High System Sensitivity |
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D Minimum Error with Large Input Signal |
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DESCRIPTION
The SST/U5545NL Series are monolithic dual n-channel JFETs designed to provide high input impedance (IG < 50 pA) for general purpose differential amplifiers. The U5545NL features minimum system error and calibration (5-mV offset maximum).
Pins 4 and 8 on the SST series and pin 4 on the U series part numbers enable the substrate to be connected to a positive, external bias (VDD) to avoid latchup.
Narrow Body SOIC
S1 |
1 |
8 |
SUBSTRATE |
D1 |
2 |
7 |
G2 |
G1 |
3 |
6 |
D2 |
SUBSTRATE |
4 |
5 |
S2 |
Top View
Marking Codes:
SST5546NL - (5546NL)
SST5547NL - (5547NL)
The SST5546NL/47NL in the SO-8 package provide ease of manufacturing. The symmetrical pinout prevents improper orientation. These part number are available with tape-and-reel options for compatibility with automatic assembly methods.
The hermetically sealed TO-78 package is available with full military processing.
TO-78
S1 |
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G2 |
1 |
7 |
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D1 2 |
6 |
D2 |
3 |
5 |
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G1 |
4 |
S2 |
CASE, SUBSTRATE
Top View
U5545NL
U5546NL
U5547NL
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Lead Temperature (1/16” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 200_C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C
Power Dissipation : |
Per Sidea . . . . . . . . . . . . . . . . . . . . . . . . |
250 mW |
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Totalb . . . . . . . . . . . . . . . . . . . . . . . . . . . |
500 mW |
Notes
a.Derate 2 mW/_C above 25_C
b.Derate 4 mW/_C above 25_C
Document Number: 72119 |
www.vishay.com |
S-03162—Rev. A, 14-Feb-03 |
7-1 |
SST/U5545NL Series
Vishay Siliconix |
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New Product |
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SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED) |
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Limits |
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U5545NL |
SST/U5546NL |
SST/U5547NL |
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Typa |
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Parameter |
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Symbol |
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Test Conditions |
Min |
Max |
Min |
Max |
Min |
Max |
Unit |
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Static |
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Gate-Source |
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V(BR)GSS |
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IG = -1 mA, VDS = 0 V |
-57 |
-50 |
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-50 |
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-50 |
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Breakdown Voltage |
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V |
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Gate-Source |
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VGS(off) |
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VDS = 15 V, ID = 0.5 nA |
-2 |
-0.5 |
-4.5 |
-0.5 |
-4.5 |
-0.5 |
-4.5 |
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Cutoff Voltage |
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Saturation Drain Currentb |
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I |
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V |
DS |
= 15 V, V |
GS |
= 0 V |
3 |
0.5 |
8 |
0.5 |
8 |
0.5 |
8 |
mA |
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DSS |
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Gate Reverse Current |
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IGSS |
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VGS = -30 V, VDS = 0 V |
-10 |
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-100 |
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-100 |
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-100 |
pA |
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TA = 150_C |
-20 |
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-150 |
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-150 |
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-150 |
nA |
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Gate Operating Current |
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IG |
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VDG = 15 V, ID = 200 mA |
-3 |
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-50 |
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-50 |
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-50 |
pA |
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Gate-Source |
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VGS(F) |
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IG = 1 mA , VDS = 0 V |
0.7 |
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V |
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Forward Voltage |
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Dynamic |
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Common-Source Forward |
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gfs |
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2.5 |
1.5 |
6.0 |
1.5 |
6.0 |
1.5 |
6.0 |
mS |
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Transconductanceb |
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VDS |
= 15 V, VGS = 0 V |
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Common-Source |
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gos |
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f = 1 kHz |
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2 |
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25 |
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25 |
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25 |
mS |
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Output Conductanceb |
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Common-Source |
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Ciss |
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3.5 |
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6 |
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6 |
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6 |
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Input Capacitance |
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VDS |
= 15 V, VGS = 0 V |
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pF |
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Common-Source Reverse |
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Crss |
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f = 1 MHz |
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1.3 |
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2 |
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2 |
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2 |
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Transfer Capacitance |
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Equivalent Input |
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V |
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= 15 V, I |
= 200 mA |
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nV⁄ |
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Noise Voltage |
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en |
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DS |
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f = 10DHz |
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20 |
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180 |
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√Hz |
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Noise Figure |
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NF |
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RG = 1 MW |
0.1 |
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3.5 |
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dB |
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Matching |
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Differential |
|VGS1 * VGS2| |
VDG = 15 V, ID = 50 mA |
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5 |
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10 |
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15 |
mV |
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Gate-Source Voltage |
VDG = 15 V, ID = 200 mA |
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5 |
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10 |
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15 |
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Gate-Source Voltage |
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D|V |
GS1 |
– V |
GS2 |
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V |
DG |
= 15 V, I |
= 200 mA |
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mV/ |
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Differential Change |
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D |
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10 |
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20 |
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40 |
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with Temperature |
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DT |
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TA = -55 to 125_C |
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_C |
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Saturation Drain |
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IDSS1 |
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V |
DS |
= 15 V, V |
GS |
= 0 V |
0.98c |
0.95 |
1 |
0.9 |
1 |
0.9 |
1 |
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Current Ratioc |
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IDSS2 |
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c |
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gfs1 |
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V |
DS |
= 15 V, I |
= 200 mA |
c |
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D |
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Transconductance Ratio |
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0.99 |
0.97 |
1 |
0.95 |
1 |
0.9 |
1 |
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gfs2 |
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f = 1 kHz |
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Notes |
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a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. |
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NQP |
b.Pulse test: PW v300 ms duty cycle v3%.
c.Assumes smaller value in the numerator.
www.vishay.com |
Document Number: 72119 |
7-2 |
S-03162—Rev. A, 14-Feb-03 |