Vishay SST5546NL, SST5547NL, U5545NL, U5546NL, U5547NL Schematic [ru]

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Vishay SST5546NL, SST5547NL, U5545NL, U5546NL, U5547NL Schematic

 

SST/U5545NL Series

New Product

Vishay Siliconix

Monolithic N-Channel JFET Duals

PRODUCT SUMMARY

 

 

 

 

 

 

 

 

 

 

Part Number

VGS(off) (V)

V(BR)GSS Min (V)

gfs Min (mS)

IG Max (pA)

jVGS1 - VGS2j Max (mV)

U5545NL

-0.5 to -4.5

-50

1.5

-50

5

 

 

 

 

 

 

SST/U5546NL

-0.5 to -4.5

-50

1.5

-50

10

 

 

 

 

 

 

SST/U5547NL

-0.5 to -4.5

-50

1.5

-50

15

 

 

 

 

 

 

FEATURES

BENEFITS

APPLICATIONS

D Anti Latchup Capability

D External Substrate Bias—Avoids Latchup

D Wideband Differential Amps

D Monolithic Design

D Tight Differential Match vs. Current

D High-Speed, Temp-Compensated,

D High Slew Rate

D Improved Op Amp Speed, Settling Time

Single-Ended Input Amps

D Low Offset/Drift Voltage

Accuracy

D High-Speed Comparators

D Low Gate Leakage: 3 pA

D Minimum Input Error/Trimming Requirement

D Impedance Converters

D Low Noise

D Insignificant Signal Loss/Error Voltage

 

D High CMRR: 100 dB

D High System Sensitivity

 

 

D Minimum Error with Large Input Signal

 

DESCRIPTION

The SST/U5545NL Series are monolithic dual n-channel JFETs designed to provide high input impedance (IG < 50 pA) for general purpose differential amplifiers. The U5545NL features minimum system error and calibration (5-mV offset maximum).

Pins 4 and 8 on the SST series and pin 4 on the U series part numbers enable the substrate to be connected to a positive, external bias (VDD) to avoid latchup.

Narrow Body SOIC

S1

1

8

SUBSTRATE

D1

2

7

G2

G1

3

6

D2

SUBSTRATE

4

5

S2

Top View

Marking Codes:

SST5546NL - (5546NL)

SST5547NL - (5547NL)

The SST5546NL/47NL in the SO-8 package provide ease of manufacturing. The symmetrical pinout prevents improper orientation. These part number are available with tape-and-reel options for compatibility with automatic assembly methods.

The hermetically sealed TO-78 package is available with full military processing.

TO-78

S1

 

G2

1

7

 

D1 2

6

D2

3

5

 

G1

4

S2

CASE, SUBSTRATE

Top View

U5545NL

U5546NL

U5547NL

ABSOLUTE MAXIMUM RATINGS

Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Lead Temperature (1/16” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 200_C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C

Power Dissipation :

Per Sidea . . . . . . . . . . . . . . . . . . . . . . . .

250 mW

 

Totalb . . . . . . . . . . . . . . . . . . . . . . . . . . .

500 mW

Notes

a.Derate 2 mW/_C above 25_C

b.Derate 4 mW/_C above 25_C

Document Number: 72119

www.vishay.com

S-03162—Rev. A, 14-Feb-03

7-1

SST/U5545NL Series

Vishay Siliconix

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

New Product

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Limits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U5545NL

SST/U5546NL

SST/U5547NL

 

 

 

 

 

 

 

 

 

 

 

 

 

Typa

 

 

 

 

 

 

 

Parameter

 

Symbol

 

 

Test Conditions

Min

Max

Min

Max

Min

Max

Unit

Static

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate-Source

 

 

V(BR)GSS

 

 

 

IG = -1 mA, VDS = 0 V

-57

-50

 

-50

 

-50

 

 

Breakdown Voltage

 

 

 

 

 

 

 

 

V

Gate-Source

 

 

VGS(off)

 

 

VDS = 15 V, ID = 0.5 nA

-2

-0.5

-4.5

-0.5

-4.5

-0.5

-4.5

 

 

 

 

 

Cutoff Voltage

 

 

 

 

 

Saturation Drain Currentb

 

 

 

I

 

 

 

 

 

 

V

DS

= 15 V, V

GS

= 0 V

3

0.5

8

0.5

8

0.5

8

mA

 

 

 

 

DSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate Reverse Current

 

 

 

IGSS

 

 

 

 

VGS = -30 V, VDS = 0 V

-10

 

-100

 

-100

 

 

-100

pA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA = 150_C

-20

 

-150

 

-150

 

 

-150

nA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate Operating Current

 

 

 

 

IG

 

 

 

 

VDG = 15 V, ID = 200 mA

-3

 

-50

 

-50

 

 

-50

pA

Gate-Source

 

 

VGS(F)

 

 

 

 

 

IG = 1 mA , VDS = 0 V

0.7

 

 

 

 

 

 

 

V

Forward Voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dynamic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Common-Source Forward

 

 

 

gfs

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5

1.5

6.0

1.5

6.0

1.5

6.0

mS

Transconductanceb

 

 

 

 

 

 

 

VDS

= 15 V, VGS = 0 V

Common-Source

 

 

 

gos

 

 

 

 

 

 

 

 

 

f = 1 kHz

 

2

 

25

 

25

 

 

25

mS

Output Conductanceb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Common-Source

 

 

 

Ciss

 

 

 

 

 

 

 

 

 

 

 

 

 

3.5

 

6

 

6

 

 

6

 

Input Capacitance

 

 

 

 

 

 

 

VDS

= 15 V, VGS = 0 V

 

 

 

 

pF

Common-Source Reverse

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Crss

 

 

 

 

 

 

 

 

 

f = 1 MHz

 

1.3

 

2

 

2

 

 

2

 

Transfer Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Equivalent Input

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

= 15 V, I

= 200 mA

 

 

 

 

 

 

 

 

nV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Noise Voltage

 

 

 

 

en

 

 

 

 

 

DS

 

f = 10DHz

 

20

 

180

 

 

 

 

 

Hz

Noise Figure

 

 

 

NF

 

 

 

 

 

 

 

 

 

 

 

RG = 1 MW

0.1

 

3.5

 

 

 

 

 

dB

Matching

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Differential

|VGS1 * VGS2|

VDG = 15 V, ID = 50 mA

 

 

5

 

10

 

 

15

mV

Gate-Source Voltage

VDG = 15 V, ID = 200 mA

 

 

5

 

10

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate-Source Voltage

 

D|V

GS1

– V

GS2

|

 

V

DG

= 15 V, I

= 200 mA

 

 

 

 

 

 

 

 

mV/

Differential Change

 

 

 

 

 

 

 

 

D

 

 

 

 

10

 

20

 

 

40

 

with Temperature

 

 

 

DT

 

 

 

 

 

 

 

TA = -55 to 125_C

 

 

 

 

 

 

 

 

_C

Saturation Drain

 

 

 

IDSS1

 

 

 

V

DS

= 15 V, V

GS

= 0 V

0.98c

0.95

1

0.9

1

0.9

1

 

Current Ratioc

 

 

 

IDSS2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c

 

 

 

 

gfs1

 

 

 

 

V

DS

= 15 V, I

= 200 mA

c

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

Transconductance Ratio

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.99

0.97

1

0.95

1

0.9

1

 

 

 

 

 

gfs2

 

 

 

 

 

 

 

 

 

f = 1 kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

 

 

 

 

 

 

 

NQP

b.Pulse test: PW v300 ms duty cycle v3%.

c.Assumes smaller value in the numerator.

www.vishay.com

Document Number: 72119

7-2

S-03162—Rev. A, 14-Feb-03

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