Vishay SST5198NL, SST5199NL, U5196NL, U5197NL, U5198NL Schematic [ru]

SST/U5196NL Series

				New Product			Vishay Siliconix
			Monolithic N-Channel JFET Duals
					SST5198NL		U5196NL	U5198NL
					SST5199NL		U5197NL	U5199NL
PRODUCT SUMMARY
Part Number	VGS(off) (V)		V(BR)GSS Min (V)	gfs Min (mS)	IG Max (pA)	jVGS1 - VGS2j Max (mV)
U5196NL		-0.7 to -4	-50	1	-15		5
U5197NL		-0.7 to -4	-50	1	-15		5
SST/U5198NL		-0.7 to -4	-50	1	-15		10
SST/U5199NL		-0.7 to -4	-50	1	-15		15
FEATURES			BENEFITS				APPLICATIONS
D Anti Latchup Capability			D External Substrate Bias—Avoids Latchup				D Wideband Differential Amps
D Monolithic Design			D Tight Differential Match vs. Current				D High-Speed, Temp-Compensated,
D High Slew Rate			D Improved Op Amp Speed, Settling Time Accuracy				Single-Ended Input Amps
D Low Offset/Drift Voltage			D Minimum Input Error/Trimming Requirement				D High Speed Comparators
D Low Gate Leakage: 5 pA			D Insignificant Signal Loss/Error Voltage				D Impedance Converters
D Low Noise			D High System Sensitivity
D High CMRR: 100 dB			D Minimum Error with Large Input Signal

DESCRIPTION

The SST/U5196NL series of JFET duals are designed for high-performance differential amplification for a wide range of precision test instrumentation applications. This series features tightly matched specs, low gate leakage for accuracy, and wide dynamic range with IG guaranteed at VDG = 20 V.

The U series in the hermetically-sealed TO-78 package is available with full military processing. The SST series SO-8 package provides ease of manufacturing and the symmetrical pinout prevents improper orientation. The SO-8 package is available with tape-and-reel options for compatibility with automatic assembly methods.

Pins 4 and 8 of the SST series and pin 4 on the U series part numbers enable the substrate to be connected to a positive, external bias (VDD) to avoid latchup.

For similar products see the low-noise SST/U401NL series and the low-leakage U421NL/423NL data sheets.

TO-78

	Narrow Body SOIC
S1	1	8	SUBSTRATE		S1	G2
D1			G2
	2	7			1	7
G1	3	6	D2
SUBSTRATE	4	5	S2	D1	2	6	D2
		Top View			3	5
					G1	4	S2
		Marking Codes:
						CASE, SUBSTRATE
		SST5198NL - 5198NL
						Top View
		SST5199NL - 5199NL
					U5196NL, U5198NL
					U5197NL, U5199NL

ABSOLUTE MAXIMUM RATINGS

Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Lead Temperature (1/16” from case for 10 sec.) . . . . . . . . . . . . . . . . . . 300 _C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 200_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C

Power Dissipation :	Per Sidea . . . . . . . . . . . . . . . . . . . . . . . .	250 mW
	Totalb . . . . . . . . . . . . . . . . . . . . . . . . . . .	500 mW

Notes

a.Derate 2 mW/_C above 85_C

b.Derate 4 mW/_C above 85_C

Document Number: 72156	www.vishay.com
S-03468—Rev. B, 11-Mar-03	7-1

SST/U5196NL Series

Vishay Siliconix

New Product

SPECIFICATIONS FOR U5196NL AND U5197NL (TA = 25_C UNLESS OTHERWISE NOTED)

Limits

U5196NL

U5197NL

Typa

Parameter

Symbol

Test Conditions

Min

Max

Min

Max

Unit

Static

Gate-Source Breakdown Voltage

V(BR)GSS

IG = -1 mA, VDS = 0 V

-57

-50

-50

V

Gate-Source Cutoff Voltage

VGS(off)

VDS = 20 V, ID = 1 nA

-2

-0.7

-4

-0.7

-4

Saturation Drain Currentb

IDSS

VDS = 20 V, VGS = 0 V

3

0.7

7

0.7

7

mA

Gate Reverse Current

IGSS

VGS = -30 V, VDS = 0 V

-10

-25

-25

pA

TA = 150_C

-20

-50

-50

nA

Gate Operating Current

IG

VDG = 20 V, ID = 200 mA

-5

-15

-15

pA

TA = 125_C

-0.8

-15

-15

nA

Gate-Source Voltage

VGS

VDG = 20 V, ID = 200 mA

-1.5

-0.2

-3.8

-0.2

-3.8

V

Dynamic

Common-Source

gfs

3.0

1

4

1

4

mS

Forward Transconductance

VDS

= 20 V, VGS = 0 V

Common-Source

gos

f = 1 kHz

8

50

50

mS

Output Conductance

Common-Source

gfs

0.8

0.7

1.6

0.7

1.6

mS

Forward Transconductance

VDS = 20 V, ID = 200 mA

Common-Source

gos

f = 1 kHz

1

4

4

mS

Output Conductance

Common-Source

Ciss

3

6

6

Input Capacitance

VDS

= 20 V, VGS = 0 V

pF

Common-Source

Crss

f = 1 MHz

1

2

2

Reverse Transfer Capacitance

nV⁄

Equivalent Input Noise Voltage

en

VDS = 20 V, VGS = 0 V, f = 1 kHz

11

20

20

√Hz

Noise Figure

NF

VDS

= 20 V, VGS = 0 V

0.5

0.5

dB

f = 100 Hz, RG = 10 MW

Matching

Differential Gate-Source Voltage

|VGS1–VGS2|

VDG = 20 V, ID = 200 mA

5

5

mV

Gate-Source Voltage Differential

D|V

GS1

–V

GS2

|

V

DG

= 20 V, I = 200 mA

_

D

5

10

Change with Temperature

TA = -55 to 125_C

mV/ C

DT

Saturation Drain Current Ratio

IDSS1

VDS = 20 V, VGS = 0 V

0.98

0.95

1

0.95

1

IDSS2

Transconductance Ratio

gfs1

0.99

0.97

1

0.97

1

gfs2

VDS = 20 V, ID = 200 mA

Differential Output Conductance

|gos1–gos2|

f = 1 kHz

0.1

1

1

mS

Differential Gate Current

|IG1 *IG2|

VDG = 20 V, ID = 200 mA , TA = 125_C

0.1

5

5

nA

Common Mode Rejection Ratio

CMRR

VDG = 10 to 20 V, ID = 200 mA

100

dB

www.vishay.com	Document Number: 72156
7-2	S-03468—Rev. B, 11-Mar-03

SST/U5196NL Series

New Product

Vishay Siliconix

SPECIFICATIONS FOR SST/U5198NL AND SST/U5199NL

(TA = 25_C UNLESS OTHERWISE NOTED)

Limits

SST/U5198NL

SST/U5199NL

Typa

Parameter

Symbol

Test Conditions

Min

Max

Min

Max

Unit

Static

Gate-Source Breakdown Voltage

V(BR)GSS

IG = -1 mA, VDS = 0 V

-57

-50

-50

V

Gate-Source Cutoff Voltage

VGS(off)

VDS = 20 V, ID = 1 nA

-2

-0.7

-4

-0.7

-4

Saturation Drain Currentb

IDSS

VDS = 20 V, VGS = 0 V

3

0.7

7

0.7

7

mA

Gate Reverse Current

IGSS

VGS = -30 V, VDS = 0 V

-10

-25

-25

pA

TA = 150_C

-20

-50

-50

nA

Gate Operating Current

IG

VDG = 20 V, ID = 200 mA

-5

-15

-15

pA

TA =125_C

-0.8

-15

-15

nA

Gate-Source Voltage

VGS

VDG = 20 V, ID = 200 mA

-1.5

-0.2

-3.8

-0.2

-3.8

V

Dynamic

Common-Source

gfs

3.0

1

4

1

4

mS

Forward Transconductance

VDS = 20 V, VGS = 0 V, f = 1 kHz

Common-Source

gos

8

50

50

mS

Output Conductance

Common-Source

gfs

0.8

0.7

1.6

0.7

1.6

mS

Forward Transconductance

VDS = 20 V, ID = 200 mA

Common-Source

gos

f = 1 kHz

1

4

4

mS

Output Conductance

Common-Source Input Capacitance

Ciss

3

6

6

VDS = 20 V, VGS = 0 V, f = 1 MHz

pF

Common-Source

Crss

1

2

2

Reverse Transfer Capacitance

nV⁄

Equivalent Input Noise Voltage

en

VDS = 20 V, VGS = 0 V, f = 1 kHz

11

√Hz

Noise Figure

NF

VDS = 20 V, VGS = 0 V

0.5

dB

f = 100 Hz, RG = 10 MW (U Only)

Matching

Differential Gate-Source Voltage

|VGS1–VGS2|

VDG = 20 V, ID = 200 mA

10

15

mV

D|VGS1–VGS2|

SST5198NL

15

Gate-Source Voltage Differential

VDG = 20 V, ID = 200 mA

SST5199NL

30

mV/_C

Change with Temperature

DT

TA = -55 to 125_C

U Only

20

40

Saturation Drain Current Ratio

|

IDSS1

|

VDS = 20 V, VGS = 0 V

SST Only

0.97

U Only

0.95

1

0.95

1

IDSS2

Transconductance Ratio

gfs1

SST Only

0.97

mS

U Only

0.95

1

0.95

1

gfs2

V

DS

= 20 V, I = 200 mA

D

Differential Output Conductance

|gos1–gos2|

f = 1 kHz

SST Only

0.2

U Only

1

1

Differential Gate Current

|IG1 *IG2|

VDG

= 20 V, ID = 200 mA,

SST Only

0.1

nA

T = 125_C

U Only

5

5

A

Common Mode Rejection Ratio

CMRR

VDG = 10 to 20 V, ID = 200 mA

97

dB

Notes

a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

NQP

b.Pulse test: PW v300 ms duty cycle v3%.

Document Number: 72156	www.vishay.com
S-03468—Rev. B, 11-Mar-03	7-3