Vishay SST404NL, SST406NL, U401NL, U404NL, U406NL Schematic [ru]

SST/U401NL Series

			New Product				Vishay Siliconix
		Monolithic N-Channel JFET Duals
				SST404NL		U401NL		U406NL
				SST406NL		U404NL
PRODUCT SUMMARY
Part Number		VGS(off) (V)	V(BR)GSS Min (V)	gfs Min (mS)	IG Typ (pA)		jVGS1 - VGS2j Max (mV)
U401NL		-0.5 to -2.5	-40	1	-2			5
SST/U404NL		-0.5 to -2.5	-40	1	-2			15
SST/U406NL		-0.5 to -2.5	-40	1	-2			40

	FEATURES	BENEFITS	APPLICATIONS
	D Anti Latchup Capability	D External Substrate Bias—Avoids Latchup	D Wideband Differential Amps
	D Monolithic Design	D Tight Differential Match vs. Current	D High-Speed,Temp-Compensated,
	D High Slew Rate	D Improved Op Amp Speed, Settling Time Accuracy	Single-Ended Input Amps
	D Low Offset/Drift Voltage	D Minimum Input Error/Trimming Requirement	D High-Speed Comparators
			D Impedance Converters
	D Low Gate Leakage: 2 pA	D Insignificant Signal Loss/Error Voltage
	D Low Noise	D High System Sensitivity
	D High CMRR: 102 dB	D Minimum Error with Large Input Signal
	DESCRIPTION

The SST/U401NL series of high-performance monolithic dual JFETs features extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications. This series has a wide selection of offset and drift specifications with the U401NL featuring a 5-mV offset and 10-mV/_C drift.

Pins 4 and 8 of the SST series, and pin 4 of the U series part

numbers enable the substrate to be connected to a positive polarity, external bias (VDD) to avoid latchup.

The U series, hermetically sealed TO-78 package is available with full military processing. The SST series SO-8 package provides ease of manufacturing, and the symmetrical pinout prevents improper orientation. The SO-8 package is available with tape-and-reel options for compatibility with automatic assembly methods.

							TO-78
		Narrow Body SOIC				S1		G2
	S1	1	8	SUBSTRATE		1	7
	D1	2	7	G2	D1	2	6	D2
	G1	3	6	D2
	SUBSTRATE	4	5	S2		3	5
						G1	4	S2
			Top View				CASE, SUBSTRATE
			Marking Codes:				Top View
			SST404NL - 404NL				U401NL
			SST406NL - 406NL				U404NL
							U406NL

ABSOLUTE MAXIMUM RATINGS

Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Lead Temperature (1/16” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C

Storage Temperature : U Prefix . . . . . . . . . . . . . . . . . . . . . -65 to 200_C SST Prefix . . . . . . . . . . . . . . . . . . . -55 to 150_C

For applications information see AN106.

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C

Power Dissipation : Per Sidea . . . . . . . . . . . . . . . . . . . . . . . . 300 mW Totalb . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW

Notes

a.Derate 2.4 mW/_C above 25_C

b.Derate 4 mW/_C above 25_C

Document Number: 72055	www.vishay.com
S-22448—Rev. A, 17-Feb-03	7-1

SST/U401NL Series

Vishay Siliconix

New Product

SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)

Limits

U401NL

SST/U404NL

SST/U406NL

Typa

Parameter

Symbol

Test Conditions

Min

Max

Min

Max

Min

Max

Unit

Static

Gate-Source

V(BR)GSS

IG = -1 mA, VDS = 0 V

-58

-40

-40

-40

Breakdown Voltage

V(BR)G1 - G2

IG = "1 mA, VDS = 0 V, VGS = 0 V

"45

"30

"30

"30

V

Gate-Source

VGS(off)

VDS = 15 V, ID = 1 nA

-1.5

-0.5

-2.5

-0.5

-2.5

-0.5

-2.5

Cutoff Voltage

Saturation

IDSS

VDS = 10 V, VGS = 0 V

3.5

0.5

10

0.5

10

0.5

10

mA

Drain Currentb

Gate Reverse Current

IGSS

VGS = -30 V, VDS = 0 V

-2

-25

-25

-25

pA

TA = 125_C

-1

nA

Gate Operating

IG

VDG = 15 V, ID = 200 mA

-2

-15

-15

-15

pA

Current

_

-0.8

-10

-10

-10

nA

TA = 125 C

Drain-Source

rDS(on)

VGS = 0 V, ID = 0.1 mA

250

W

On-Resistance

Gate-Source Voltage

VGS

VDG = 15 V, ID = 200 mA

-1

-2.3

-2.3

-2.3

V

Gate-Source

VGS(F)

IG = 1 mA , VDS = 0 V

0.7

Forward Voltage

Dynamic

Common-Source

gfs

1.5

1

2

1

2

1

2

mS

Forward

VDS = 15 V, ID = 200 mA

Transconductance

f = 1 kHz

Common-Source

gos

1.3

2

2

2

mS

Output Conductance

Common-Source

gfs

4

2

7

2

7

2

7

mS

Forward

VDS = 10 V, VGS = 0 V

Transconductance

f = 1 kHz

Common-Source

gos

5

30

30

30

mS

Output Conductance

Common-Source

Ciss

4

8

8

8

Input Capacitance

VDS = 15 V, ID = 200 mA

pF

Common-Source

Crss

f = 1 MHz

1.5

3

3

3

Reverse Transfer

Capacitance

Equivalent Input

VDS = 15 V, ID = 200 mA

nV⁄

en

10

20

20

20

Noise Voltage

f = 10 Hz (U Only)

√Hz

Matching

Differential

|VGS1 – VGS2|

VDG = 10 V, ID = 200 mA

5

15

40

mV

Gate-Source Voltage

Gate-Source Voltage

D|V

– V

|

VDG = 10 V

SST404NL

20

GS1

GS2

Differential Change

ID = 200 mA

SST406NL

40

mV/_C

DT

with Temperature

TA = -55 to 125_C

All U

10

25

80

Common Mode

CMRR

VDG = 10 to 20 V, ID = 200 mA

102

95

95

dB

Rejection Ratio

Notes

a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

NNR

b.Pulse test: PW v300 ms duty cycle v3%.

www.vishay.com	Document Number: 72055
7-2	S-22448—Rev. A, 17-Feb-03