V3 Semiconductor V363EPC-50REVA0 Datasheet

V363EPC A0 Local Bus to PCI Bridge

for Embedded Processors

1.0 About the V363EPC

V363EPC A0 Data Sheet

▼ Direct interface to these processors:

• AMD

AM29030/40™

• IBM

PowerPC 401™ Gx

• Intel

i960® Cx/Hx/Jx/Sx

▼ Fully compliant with PCI Local Bus

Specification, Revision 2.1

▼ Configurable for system master, PCI bus

master, or PCI target operation

▼ Type 0 and Type 1 PCI configuration cycles ▼ Up to 1 kB burst access on the PCI or

the local bus

▼ 640 bytes of programmable FIFO storage with

Dynamic Bandwidth Allocation™ architecture

▼ 64-byte read FIFO in each direction ▼ Enhanced support for 8-bit/16-bit local bus

devices with programmable region sizes

▼ Dual bi-directional address space remapping ▼ 10-bit bus watch timer ▼ On-the-fly byte order (endian) conversion

▼ I

O-Ready™ ATU and messaging unit,

including hardware controlled circular queues

▼ Two-channel DMA, multiprocessor DMA

chaining, and demand mode DMA

▼ Hot Swap Capable™ according to the PICMG

Hot Swap Specification, version 2.1

▼ Sixteen 8-bit bi-directional mailbox registers

with doorbell interrupts

▼ Support for real-mode MS-DOS

holes

▼ Flexible PCI and local interrupt management ▼ Optional power-on serial EEPROM

initialization

▼ Up to 50 MHz on both PCI and local bus clocks ▼ 3.3 V operation; 5 V tolerant input ▼ Industrial temperature range (−40°C to +85°C) ▼ Low-cost 160-pin EIAJ PQFP package

(Electronic Industries Association of Japan Plastic Quad Flat Pack)

About the V363EPC

The V363EPC offers the highest performance, most flexible, and most economical solution for interfacing either 32-bit or 16-bit local bus applications to the PCI bus. It is also an ideal candidate for a variety of high-performance applications based on Motorola, IBM, DEC, Hitachi, and other popular embedded processors where only a minimal amount of glue logic is needed.

V363EPC is the 3.3 V enhanced version of the V350EPC and V360EPC Rev A1 devices and supports powerful features like Hot Swap and DMA chaining. The PCI bus operates at up to 50 MHz, independent of local bus clock frequency. The overall throughput of the system is dramatically improved by using our unique Dynamic Bandwidth Allocation™ architecture.

Access to the PCI bus can be performed through two programmable address apertures. Two more apertures are provided for PCI-to-local bus accesses. There are 64 bytes of read FIFOs in each direction, 32 bytes dedicated for each aperture.

Two high-performance DMA channels with chaining and demand mode capabilities provide a powerful data transfer engine for bulk data transfers. Mailbox registers and flexible PCI interrupt controllers also provide a simple mechanism to emulate PCI device control ports. The part is available in a 160-pin, low-cost PQFP package.

This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V363EPC. Detailed functional information is contained in the User’s Manual.

Note:

V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.

Product Codes

Figure 1: Example Applications

2.0 Product Codes

Table 1: Product Codes

Product Code Package Frequency

V363EPC-50 REV A0 160-pin EIAJ PQFP 50 MHz

CPU

PCI Edge Connector

SCSI

Controller

Card acts as a bus master; it receives and transmits data on the PCI bus

Hard

Disk

Graphics

Engine

PCI Edge Connector

Frame Buffer

and RAMDAC

Card is never a bus master and receives video data from other masters

Monitor

V363EPC

CPU

PCI Bus

PCI T arget

Add-In

Card

PCI T arget

Add-In

Card

PCI T arget

Add-In

Card

V363EPC

V380SDC

SDRAM

Controller

PCI Bus

SDRAM

V363EPC

2O Ready

V363EPC

2O Ready

Pin Descriptions and Pinouts

3.0 Pin Descriptions and Pinouts

Table 2 lists the pin types found on the V363EPC. Together, Tab l e 3 and Tab l e 4 describe the function of each pin on

the V363EPC. Table 5 lists the RESET state for test mode pins. Section 3.2 lists processor-mode-specific pin assignments and shows the pinouts for the 160-pin EIAJ PQFP package. Figure 6 shows the mechanical dimensions of the package.

Tabl e 2 : Pin Types

Pin T ype Description

PCI I PCI input only pin.

PCI O PCI output only pin.

PCI I/O PCI tri-state I/O pin.

PCI I/O

PCI input with open drain output.

I/O

TTL I/O pin with 4 mA output drive.

I TTL input only pin.

TTL output pin with 4 mA output drive.

Table 3: Signal Descriptions: Non-Processor Mode Dependent

Signal Type

Reset

State

Description

PCI Bus Interface Signals

AD[31:0] PCI I/O Z

Address and Data

multiplexed on the same pins.

C/BE[3:0] PCI I/O Z

Bus Command and Byte Enables

multiplexed on the same pins.

PAR PCI I/O Z

Parity

represents even parity across AD[31:0] and C/BE

[3:0].

FRAME PCI I/O Z

Cycle Frame

indicates the beginning and burst length of an access.

IRDY

PCI I/O Z

Initiator R e a dy

indicates the initiating agent’s (bus master’ s ) ability

to complete the current data phase of the transaction.

TRDY PCI I/O Z

Target Ready

indicates the target agent’s (selected device’s) ability

to complete the current data phase of the transaction.

STOP

PCI I/O Z

Stop

indicates that the current target is requesting the master to stop

the current transaction (retry or disconnect).

DEVSEL PCI I/O Z

Device Select

, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL

indicates whether any device on

the bus has been selected.

Pin Descriptions and Pinouts

IDSEL PCI I

Initialization Device Select

is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip’s internal configuration space.

REQ PCI O Z

Request

indicates to the arbiter that this agent requests use of the

bus.

GNT

PCI I

Grant

indicates to the agent that access to the bus has been

granted.

PCLK PCI I

PCI Clock

provides timing for all transactions on the PCI bus.

PRST

PCI I/O Z/L

PCI Reset

acts as an input when RDIR is high, an output when RDIR is low. As an input it is asserted low to bring all internal EPC operation to a reset state.

PERR PCI I/O Z

Parity Err or

is used to report data parity errors during al l PCI

transactions except a Special Cycle.

SERR

PCI I/OD Z

System Error

is used to report address parity errors, data par ity errors on the Special Cycle command, or any other system error where the result will be catastrophic.

INT[A:D] PCI I/OD Z

Interrupt

is used to receive or generate level-sensitive interrupt

requests.

Serial EEPROM Interface Signals

SCL/LPERR O

EEPROM Clock, Local Parity Error.

SDA I/O

EEPROM D a ta

Configuration Signal

RDIR I

Reset Direction

: tie low to drive PRST

out and LRST in; tie high to

drive LRST

out and PRST in.

Power and Ground Signals

—

Power

leads for external connection to a 3.3 V VCC board plane.

GND —

Ground

leads for external connection to a GND board plane.

Table 3: Signal Descriptions: Non-Processor Mode Dependent

Signal Type

Reset

State

Description

Pin Descriptions and Pinouts

Table 4: Signal Descriptions: Processor Mode Dependent

De-Multiplexed A/D M ultiplexed A/D

Type

Reset

State

Description

AM29030/40 i960Cx/Hx i960Jx i960Sx

ID[31:0] LD[31:0] LAD[31:0] LAD[15:0] I/O

De-multiplexed data bus. Multiplexed address and data bus.

LA[31:2] LA[31:2] LA[5:2]

LA[31:16]

LA[5:2]

I/O

Address Bus

LA[5:2] are output only in

Multiplexed A/D mode.

BWE

[3:0] BE[3:0] BE[3:0] BE[1:0] I/O

Byte Enables

R/W W/R W/R W/R I/O

Read-Write

strobe.

——ALEALEI/O

Address Latch Enable

LREQ ADS ADS AS I/

Address Strobe is asserted low to indicate the beginning of a bus cycle; interpreted as LREQ

in AM29030/40 mode.

RDY READY RDYRCY READY I/O

Data Ready

LBREQ HOLD HOLD HOLD O

1. The reset state is ‘H’ in AM29030/40 mode.

Bus Mastership Request

LBGRT

HOLDA HOLDA HOLDA I

Bus Mastership Grant

LPAR[3:0] LPAR[3:0] LPAR[3:0] LPAR[1:0] I/O

Data Parity

BURST

BLAST BLAST BLAST I/O

BURST

Burst Request

BLAST

Burst Last

ERR BTERM BTERM — I/

ERR:

Bus Time-out

BTERM

Burst Terminate

LINT

LINT LINT LINT O

Local Interrupt Request

LRST LRST LRST LRST I/O

L/Z

Local Bus RESET

MEMCLK LCLK LCLK LCLK I

Local Bus Clock

Pin Descriptions and Pinouts

Test Mode Pins

3.1 Test Mode Pins

Several device pins are used during the manufacturing test to put the V363EPC device into various test modes.

Note:

These pins must be maintained at proper levels during reset to insure proper

operation.

This is typically handled through pull-up or pull-down resistors (typically 1–10 kΩ) on the signal pins if they are not

guaranteed to be at the proper level during reset. Table 5 shows the reset states for test mode pins.

3.2 Processor-mode Specific Pin Assignments

The following tables and diagrams describe the pin assignments for the V363EPC A0 in its various processor modes.

• AM29030/040 mode: Table 6 and Figure 2

• i960 Cx/Hx mode: Table 7 and Figure 3

• i960 Jx mode: Table 8 and Figure 4

• i960 Sx mode: Ta b l e 9 and Figure 5

Table 5: RESET State for Test Mode Pins

Mode Pin 134 Pin 135 Pin 153

i960 Cx/Hx

Pull up Pull up Pull up

AMD 2930/40

Pull down Pull up Pull up

i960 Jx

Pull down Pull up Pull down

i960 Sx

Pull down Pull down Pull down

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