Standard Products
QCOTSTM UT7Q512 512K x 8 SRAM
Data Sheet
August, 2002
FEATURES
q100ns (5 volt supply) maximum address access time
qAsynchronous operation for compatibility with industrystandard 512K x 8 SRAMs
qTTL compatible inputs and output levels, three-state bidirectional data bus
qTypical radiation performance
-Total dose: 30krad(Si)
-30krad(Si) to 300krad(Si), depending on orbit, using Aeroflex UTMC patented shielded package
-SEL Immune >80 MeV-cm2 /mg
-LETTH(0.25) = 5MeV-cm 2/mg
-Saturated Cross Section (cm2) per bit, ~1.0E-7
-1.5E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
qPackaging options:
-32-lead ceramic flatpack (weight 2.5-2.6 grams)
qStandard Microcircuit Drawing 5962-99606
-QML T and Q compliant
INTRODUCTION
The QCOTST M UT7Q512 Quantified Commercial Off-the- Shelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected.
Writing to the device is accomplished by taking the Chip Enable One ( E) input LOW and the Write Enable ( W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then
written into the location specified on the address pins (A0 through A1 8). Reading from the device is accomplished by
taking Chip Enable One (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the eight I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected (E, HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOW and W LOW).
Clk. Gen. Pre-Charge Circuit
A0 |
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Memory Array |
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A1 |
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A2 |
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Select |
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1024 Rows |
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A3 |
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512x8 Columns |
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A5 |
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A4 |
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A6 |
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A7 |
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A8 |
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I/O Circuit |
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A9 |
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Column Select |
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DQ0 |
- DQ 7 |
Data |
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Control |
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CLK |
A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
A17 |
A18 |
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Gen. |
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E |
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W |
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G |
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Figure 1. UT7Q512 SRAM Block Diagram
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PIN NAMES |
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A(18:0) |
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Address |
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DQ(7:0) |
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Data Input/Output |
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E |
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Chip Enable |
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W |
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Write Enable |
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G |
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Output Enable |
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VDD |
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Power |
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VSS |
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Ground |
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A18 |
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NC |
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1 |
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36 |
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A16 |
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2 |
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35 |
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A15 |
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A14 |
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3 |
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34 |
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A17 |
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A12 |
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4 |
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33 |
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W |
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A7 |
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32 |
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A13 |
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A6 |
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31 |
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A8 |
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A5 |
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7 |
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A9 |
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A4 |
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8 |
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29 |
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A11 |
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VDD |
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28 |
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VS S |
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VSS |
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27 |
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VD D |
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A3 |
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26 |
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G |
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A2 |
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12 |
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25 |
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A10 |
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A1 |
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13 |
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24 |
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E |
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A0 |
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23 |
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DQ7 |
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DQ0 |
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15 |
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22 |
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DQ6 |
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DQ1 |
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16 |
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21 |
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DQ5 |
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DQ2 |
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20 |
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DQ4 |
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DQ3 |
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18 |
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19 |
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NC |
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Figure 2a. UT7Q512 100ns SRAM Shielded
Package Pinout (36)
A18 |
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1 |
32 |
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VD D |
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A16 |
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31 |
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A15 |
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A14 |
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A17 |
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A12 |
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W |
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A7 |
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A13 |
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A6 |
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A8 |
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A5 |
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7 |
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A9 |
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A4 |
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A11 |
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A3 |
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G |
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A2 |
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A10 |
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A1 |
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11 |
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E |
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A0 |
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12 |
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DQ7 |
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DQ0 |
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DQ6 |
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DQ1 |
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14 |
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DQ5 |
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DQ2 |
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DQ4 |
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VSS |
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DQ3 |
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Figure 2b. UT7Q512 100ns SRAM
Package Pinout (32)
DEVICE OPERATION
The UT7Q512 has three control inputs called Enable 1 ( E), Write Enable ( W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
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G |
W |
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E |
I/O Mode |
Mode |
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X1 |
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X |
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3-state |
Standby |
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X |
0 |
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0 |
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Data in |
Write |
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1 |
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0 |
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3-state |
Read2 |
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0 |
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1 |
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Data out |
Read |
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Notes:
1.“X” is defined as a “don’t care” condition.
2.Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min), G and E less than VIL (max) defines a read cycle. Read access time is measured from the latter of DeviceEnable, Output Enable, or valid address to valid data output.
SRAM read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable-Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable-Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or tETQV have not been satisfied.
2
WRITE CYCLE
A combination of W less than VIL(max) and E less than
VIL(max) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH(min), or when W is less than VIL(max).
Write Cycle 1, the Write Enable-Controlled A ccess in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by tWLWH when the
write is initiated by W, and by t ETWH when the write is initiated
by E. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-Controlled Access in figure 4b, is defined by a write terminated by the latter of E going inactive. The write pulse width is defined by tWLEF when the write is
initiated by W, and by tETEF when the write is initiated by the
E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state
by G, the user must wait t WLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
Table 2. Typical Radiation Hardness
Design Specifications1
Total Dose |
30 |
krad(Si) nominal |
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Heavy Ion |
1.5E-7 |
Errors/Bit-Day |
Error Rate2 |
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Notes:
1.The SRAM will not latchup during radiation exposure under recommended operating conditions.
2.9 0% worst case particle environment, Geosynchronous orbit, 100 m ils of Aluminum.
3
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL |
PARAMETER |
LIMITS |
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VDD |
DC supply voltage |
-0.5 to 7.0V |
VI/O |
Voltage on any pin |
-0.5 to 7.0V |
TSTG |
Storage temperature |
-65 to +150°C |
PD |
Maximum power dissipation |
1.0W |
TJ |
Maximum junction temperature2 |
+150°C |
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ΘJC |
Thermal resistance, junction-to-case3 |
10°C/W |
II |
DC input current |
±10 mA |
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Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.
2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3.Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
LIMITS |
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VDD |
Positive supply voltage |
4.5 to 5.5V |
TC |
Case temperature range |
-55 to +125°C |
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VIN |
DC input voltage |
0V to VDD |
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V±10%) (-55°C to +125°C)
SYMBOL |
PARAMETER |
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CONDITION |
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MIN |
MAX |
UNIT |
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VIH |
High-level input voltage |
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2.2 |
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V |
VIL |
Low-level input voltage |
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.8 |
V |
VOL |
Low-level output voltage |
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IOL = 2.1mA,VDD =4.5V |
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0.4 |
V |
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VOH |
High-level output voltage |
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IOH = -1mA,VDD =4.5V |
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2.4 |
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V |
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1 |
Input capacitance |
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¦ = 1MHz @ 0V |
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10 |
pF |
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CIN |
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1 |
Bidirectional I/O capacitance |
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¦ = 1MHz @ 0V |
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10 |
pF |
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CIO |
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IIN |
Input leakage current |
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VSS < VIN < VDD , VDD = VDD (max) |
-2 |
2 |
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IOZ |
Three-state output leakage current |
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0V < VO < VDD |
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-2 |
2 |
mA |
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VDD = VDD (max) |
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G = V DD (max) |
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I 2, 3 |
Short-circuit output current |
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0V <VO <VDD |
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-80 |
80 |
mA |
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OS |
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IDD(OP) |
Supply current operating |
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Inputs: VIL = VSS + 0.8V, |
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50 |
mA |
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@ 1MHz |
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VIH = 2.2V |
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IOUT = 0mA |
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VDD = VDD (max) |
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IDD1(OP) |
Supply current operating |
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Inputs: V IL = VSS + 0.8V, |
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100 |
mA |
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@10MHz |
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VIH = 2.2V |
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IOUT = 0mA |
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VDD = VDD (max) |
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IDD2(SB) |
Nominal standby supply current |
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Inputs: V IL = VSS |
-55°C and |
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@0MHz |
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IOUT = 0mA |
25°C |
|
35 |
mA |
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E = VDD - 0.5 |
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+125°C |
|
1 |
mA |
||
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VDD = VDD (max) |
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VIH = VDD - 0.5V |
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Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .
1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2.Supplied as a design limit but not guaranteed or tested.
3.Not more than one output may be shorted at a time for maximum duration of one second.
5