UTMC 5962R9583403VXX, 5962R9583403VXC, 5962R9583403VXA, 5962R9583403QXX, 5962R9583403QXC Datasheet

Standard Products

UT54LVDSC032 Quad Receiver

Data Sheet

April 2, 2001

FEATURES

q>155.5 Mbps (77.7 MHz) switching rates

q+340mV differential signaling

q5 V power supply

qCold Spare LVDS inputs

qTTL compatible outputs

qUltra low power CMOS technology

q8.0ns maximum propagation delay

q3.0ns maximum differential skew

qRadiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019

-Total-dose: 300 krad(Si)

-Latchup immune (LET > 111 MeV-cm2/mg)

qPackaging options:

-16-lead flatpack (dual in-line)

qStandard Microcircuit Drawing 5962-95834

-QML Q and V compliant part

qCompatible with IEEE 1596.3SCI LVDS

qCompatible with ANSI/TIA/EIA 644-1996 LVDS Standard

INTRODUCTION

The UT54LVDSC032 Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The UT54LVDSC032 accepts low voltage (340mV) differential input signals and translates them to 5V TTL output levels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (100 Ω) input failsafe. Receiver output will be HIGH for all fail-safe conditions.

The UT54LVDSC032 and companion quad line driver UT54LVDS031 provides new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications.

All LVDS pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.

RIN1+	+
RIN1-	-
RIN2+	+
RIN2-	-
RIN3+	+
RIN3-	-
RIN4+	+
RIN4-	-
EN

EN

R1 ROUT1

R2 ROUT2

R3 ROUT3

R4 ROUT4

Figure 1. UT54LVDSC032 Quad Receiver Block Diagram

	RIN1-			1		16	VDD
	RIN1+			2		15	RIN4-
	ROUT1			3	UT54LVDSC032	14	RIN4+
	EN			4		13	ROUT4
					Receiver
	ROUT2			5		12
								EN
	RIN2+			6		11	ROUT3
	RIN2-			7		10	RIN3+
				8
	VSS					9		RIN3-

Figure 2. UT54LVDSC032 Pinout

TRUTH TABLE

Enables								Input	Output
EN			EN					RIN+ - RIN-	ROUT
L			H					X	Z
All other combinations								VID > 0.1V	H
of ENABLE inputs
								VID < -0.1V	L
								Full Fail-safe	H
							OPEN/SHORT or
								Terminated
PIN DESCRIPTION
Pin No.			Name					Description
2, 6, 10, 14			RIN+					Non-inverting receiver input pin
1, 7, 9, 15			RIN-					Inverting receiver input pin
3, 5, 11, 13			ROUT					Receiver output pin
4				EN				Active high enable pin, OR-ed
								with EN
12								Active low enable pin, OR-ed
				EN
								with EN
16			VDD					Power supply pin, +5V + 10%
8			VSS					Ground pin

APPLICATIONS INFORMATION

The UT54LVDSC032 receiver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

ENABLE

1/4 UT54LVDSC032

DATA

+

RT 100Ω

INPUT

-

DATA

1/4 UT54LVDS031

OUTPUT

Figure 3. Point-to-Point Application

The UT54LVDSC032 differential line receiver is capable of detecting signals as low as 100mV, over a + 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift +1V around this center point. The +1V shifting may be the result of a ground potential difference between the driver’s ground reference and the receiver’s ground reference, the common-mode effects of coupled noise or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground).

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Receiver Fail-Safe

The UT54LVDSC32 receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to TTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal.

The receiver’s internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.

1. Open Input Pins. The UT54LVDSC032 is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs.

2.Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a three-state or poweroff condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable.

3.Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (VSS to

2.4V). It is only supported with inputs shorted and no external common-mode voltage applied.

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ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL	PARAMETER	LIMITS
VDD	DC supply voltage	-0.3 to 6.0V
VI/O	Voltage on any pin	-0.3 to (VDD + 0.3V)
TSTG	Storage temperature	-65 to +150°C
PD	Maximum power dissipation	1.25 W
TJ	Maximum junction temperature2	+150°C
ΘJC	Thermal resistance, junction-to-case3	10°C/W
II	DC input current	±10mA

Notes:

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3.Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER	LIMITS
VDD	Positive supply voltage	4.5 to 5.5V
TC	Case temperature range	-55 to +125°C
VIN	DC input voltage, receiver inputs	2.4V
	DC input voltage, logic inputs	0 to VDD for EN,	EN

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