UTMC 5962R9689104VYX, 5962R9689104VYC, 5962R9689104VYA, 5962R9689104VXX, 5962R9689104VXA Datasheet

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Standard Products

UT28F256 Radiation-Hardened 32K x 8 PROM

Data Sheet

December 2002

FEATURES

qProgrammable, read-only, asynchronous, radiationhardened, 32K x 8 memory

-Supported by industry standard programmer

q45ns and 40ns maximum address access time (-55 oC to +125 oC)

qTTL compatible input and TTL/CMOS compatible output levels

qThree-state data bus

qLow operating and standby current

-Operating: 125mA maximum @25MHz ∙ Derating: 3mA/MHz

-Standby: 2mA maximum (post-rad)

qRadiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019

-Total dose: 1E6 rad(Si)

-LETTH(0.25) ~ 100 MeV-cm2/mg

-SEL Immune >128 MeV-cm 2/mg

-Saturated Cross Section cm2 per bit, 1.0E-11

-1.2E-8 errors/device-day, Adams 90% geosynchronous

heavy ion

-Memory cell LET threshold: >128 MeV-cm 2/mg

qQML Q & V compliant part

-AC and DC testing at factory

qPackaging options:

-28-lead 50-mil center flatpack (0.490 x 0.74)

-28-lead 100-mil center DIP (0.600 x 1.4) - contact factory

qVDD: 5.0 volts + 10%

qStandard Microcircuit Drawing 5962-96891

PRODUCT DESCRIPTION

The UT28F256 amorphous silicon anti-fuse PROM is a high performance, asynchronous, radiation-hardened,

32K x 8 programmable memory device. The UT28F256 PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F256. The combination of radiation-hardness, fast access time, and low power consumption make the UT28F256 ideal for high speed systems designed for operation in radiation environments.

A(14:0)

DECODER

 

MEMORY

 

 

ARRAY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

CONTROL

 

 

 

SENSE AMPLIFIER

 

 

 

 

 

 

 

 

 

 

 

 

 

PE

 

 

 

 

 

 

DQ(7:0)

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

PROGRAMMING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1. PROM Block Diagram

1

DEVICE OPERATION

The UT28F256 has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); fifteen address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. AssertingCE causes I DD to rise to its active value and decodes the fifteen address inputs to select one of 32,768 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs.

PIN CONFIGURATION

A14

1

28

VDD

A12

2

27

PE

A7

3

26

A13

A6

4

25

A8

A5

5

24

A9

 

A4

6

23

A11

 

A3

7

22

OE

 

A2

8

21

A10

A1

9

20

CE

A0

10

19

DQ7

DQ0

11

18

DQ6

DQ1

12

17

DQ5

DQ2

13

16

DQ4

VSS

14

15

DQ3

PIN NAMES

 

 

 

A(14:0)

 

Address

 

 

 

CE

 

Chip Enable

 

OE

 

Output Enable

 

PE

 

Program Enable

 

DQ(7:0)

 

Data Input/Data Output

 

 

 

 

Table 1. Device Operation Truth Table 1

OE

PE

CE

I/O MODE

MODE

X

1

1

Three-state

Standby

0

1

0

Data Out

Read

1

0

0

Data In

Program

1

1

0

Three-state

Read 2

 

 

 

 

 

Notes:

1.“X” is defined as a “don’t care” condition.

2.Device active; outputs disabled.

ABSOLUTE MAXIMUM RATINGS 1

(Referenced to VSS)

SYMBOL

PARAMETER

LIMITS

UNITS

VDD

DC supply voltage

-0.3 to 7.0

V

VI/O

Voltage on any pin

-0.5 to (VDD + 0.5)

V

TSTG

Storage temperature

-65 to +150

°C

PD

Maximum power dissipation

1.5

W

TJ

Maximum junction temperature

+175

°C

ΘJC

Thermal resistance, junction-to-case 2

3.3

°C/W

II

DC input current

±10

mA

 

 

 

 

Notes:

1 . Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability. 2 . Test per MIL-STD-883, Method 1012, infinite heat sink.

2

UTMC 5962R9689104VYX, 5962R9689104VYC, 5962R9689104VYA, 5962R9689104VXX, 5962R9689104VXA Datasheet

RECOMMENDED OPERATING CONDITIONS

 

 

 

 

 

SYMBOL

 

PARAMETER

 

LIMITS

 

UNITS

 

 

 

 

 

VDD

 

Positive supply voltage

 

4.5 to 5.5

 

V

 

TC

 

Case temperature range

 

-55 to +125

 

°C

 

VIN

 

DC input voltage

 

0 to VDD

 

V

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(VDD = 5.0V ±10%; -55°C < TC < +125°C)

SYMBOL

PARAMETER

VIH

High-level input voltage

VIL

Low-level input voltage

VOL1

Low-level output voltage

VOL2

Low-level output voltage

VOH1

High-level output voltage

VOH2

High-level output voltage

CIN

Input capacitance

1

 

1, 4

Bidirectional I/O capacitance

CIO

 

IIN

Input leakage current

IOZ

Three-state output leakage

 

current

2,3

Short-circuit output current

IOS

 

5

Supply current operating

IDD1(OP)

@25.0MHz (40ns product)

 

 

@22.2MHz (45ns product)

IDD2(SB)

Supply current standby

post-rad

 

 

 

CONDITION

MINIMUM

MAXIMUM

UNIT

(TTL)

2.4

 

V

(TTL)

 

0.8

V

IOL = 4.0mA, VDD = 4.5V (TTL)

 

0.4

V

IOL = 200mA, VDD = 4.5V (CMOS)

 

VSS + 0.10

V

IOH = -200mA, VDD = 4.5V (CMOS)

VDD -0.1

 

V

IOH = -2.0mA, V DD = 4.5V (TTL)

2.4

 

V

¦ = 1MHz, V DD = 5.0V

 

15

pF

VIN = 0V

 

 

 

¦ = 1MHz, V DD = 5.0V

 

15

pF

VOUT = 0V

 

 

 

VIN = 0V to VDD

-5

5

mA

VO = 0V to VDD

-10

10

mA

VDD = 5.5V

 

 

 

OE = 5.5V

 

 

 

VDD = 5.5V, VO = VDD

 

90

mA

VDD = 5.5V, VO = 0V

-90

 

mA

TTL inputs levels (IOUT = 0), VIL =

 

 

 

0.2V

 

125

mA

VDD, PE = 5.5V

 

117

mA

CMOS input levels VIL = VSS +0.25V

 

2

mA

CE = VDD - 0.25 VIH = VDD - 0.25V

 

 

 

 

 

 

 

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si).

1.Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.

2.Supplied as a design limit but not guaranteed or tested.

3.Not more than one output may be shorted at a time for maximum duration of one second.

4.Functional test.

5.Derates at 3.0mA/MHz.

3

READ CYCLE

A combination of PE greater than VIH(min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output.

An address access read is initiated by a change in address inputs while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time.

The chip enable-controlled access is initiated byCE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A(14:0) appears at the data outputs DQ(7:0).

Output enable-controlled access is initiated by OE going active while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tELQV have not been satisfied.

AC CHARACTERISTICS READ CYCLE (Post-Radiation)*

(VDD = 5.0V ±10%; -55°C < TC < +125°C)

SYMBOL

PARAMETER

28F256-45

28F256-40

UNIT

 

 

MIN

MAX

MIN

MAX

 

tAVAV

Read cycle time

45

 

40

 

ns

 

 

1

 

 

 

 

 

 

tAVQV

Read access time

 

45

 

40

ns

2

Output hold time

0

 

0

 

ns

tAXQX

 

 

 

 

 

 

tGLQX

OE-controlled output enable time

0

 

0

 

ns

2

 

 

 

 

 

 

tGLQV

OE-controlled access time

 

15

 

15

ns

tGHQZ

OE-controlled output three-state time

 

15

 

15

ns

2

CE -controlled output enable time

0

 

0

 

ns

tELQX

 

 

 

 

 

 

tELQV

CE -controlled access time

 

45

 

40

ns

tEHQZ

CE-controlled output three-state time

 

15

 

15

ns

Notes:

* Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019 at 1E6 rads(Si).

1.Functional test.

2.Three-state is defined as a 400mV change from steady-state output voltage.

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