UTMC UT0.25uCRH Datasheet

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UT0.25μCRH Commercial RadHardTM Structured Array

Preliminary Data Sheet

April 2003

FEATURES

qUp to 3,000,000 usable equivalent gates using structured array architecture

qToggle rates up to 1.6 GHz

qAdvanced 0.25μ silicon gate CMOS processed in a commercial fab

qOperating voltage of 3.3V and 2.5V

qI/O buffers are 5-volt compliant

qMultiple product assurance levels available, QML Q and V, military, industrial

qRadiation hardened from 100Krads(Si) to 1 Megarad total dose available using Aeroflex UTMC’s RadHard techniques

PRODUCT DESCRIPTION

The high-performance UT0.25μ Commercial RadHardTM ASIC structured array family features densities up to 3,000,000 equivalent gates and is available in multiple quality assurance levels such as MIL-PRF-38535, QML Q and V, military and industrial grades and non-RadHard versions.

For those designs requiring stringent radiation hardness, Aeroflex UTMC’s 0.25 μ deep sub-micron process employs a special technique that enhances the total dose radiation hardness from 100Krads(Si) to 1 Megarad while maintaining circuit density and reliability. In addition, for both greater transient radiation hardness and latch-up immunity, the deep submicron process is built on epitaxial wafers.

qSEU-immune to less than 1.0E-10 errors/bits-day available using special library cells

qRobust Aeroflex UTMC Design Library of cells and macros

qDesign support for Mentor Graphics®, SynopsysT M, in Verilog and VHDL design languages on Sun and Linux workstations

qFull complement of industry standard IP cores

qConfigurable RAM compilers

qSupports cold sparing for power down applications

qPower dissipation of 0.04μW/MHz/gate at VDDCORE 2.5V and 20% duty cycle

Developed from Aeroflex UTMC’s patented architectures, the deep submicron ASIC family uses a highly efficient structured array architecture for the internal cell instantiation. Combined with state-of-the-art placement and routing tools, the area utilization and signal interconnect of transistors is maximized using five levels of metal interconnect.

The UT0.25μCRH ASIC family is supported by an extensive cell library that includes SSI, MSI, and 54XX equivalent functions, as well as configurable RAM and cores. Aeroflex UTMC’s core library includes the following functions:

Intel 80C31® equivalent

Intel 80C196® equivalent

MIL-STD-1553 functions (BRCTM, RTI, RTMP)

MIL-STD-1750 microprocessor

RISC microcontroller

Configurable RAM

 

 

Table 1. Gate Densities

 

 

DIE SIZE (Mils estimate)

 

EQUIVALENT USABLE GATES1

 

SIGNAL I/O2

 

POWER & GROUND PADS

 

 

 

245

 

276,890

 

160

 

48

313

 

501,760

 

216

 

64

374

 

757,350

 

265

 

79

426

 

1,024,000

 

308

 

92

510

 

1,524,122

 

376

 

112

578

 

2,007,040

 

431

 

129

642

 

2,524,058

 

484

 

144

699

 

3,029,402

 

530

 

158

 

 

 

 

 

 

 

Notes:

1.Based on NAND2 equivalents plus 20% routing overhead. Actual usable gate count is design-dependent.

2.Includes five pins that may or may not be reserved for JTAG boundary-scan, depending on user requirements.

Low-noise Device and Package Solutions

Separate on-chip power and ground buses are provided for internal cells and output drivers which further isolate internal design circuitry from switching noise.

In addition, Aeroflex UTMC offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring built-in isolated power and ground planes (see Table 2). These planes provide lower overall resistance/inductance through power and ground paths which minimize voltage drops during periods of heavy switching. These isolated planes also

help sustain supply voltage during dose rate events, thus preventing rail span collapse.

Flatpacks are available with up to 352 leads; PGAs are available with up to 299 pins and LGAs to 472 pins. Aeroflex UTMC’s flatpacks feature a non-conductive tie bar that helps maintain lead integrity through test and handling operations. In addition to the packages listed in Table 2, Aeroflex UTMC offers custom package development and package tooling modification services for individual requirements.

 

 

Table 2. Packages

Type

 

Package

 

Flatpack

 

68, 84, 132, 172, 196, 256, 304, 340, 352

PGA

 

281, 299

LGA

 

472

 

 

 

Notes:

1.The number of device I/O pads available may be restricted by the selected package.

2.PGA packages have one additional non-connected index pin (i.e., 84 + 1 index pin = 85 total package pins for the 85 PGA). Contact Aeroflex UTMC for specific package drawings.

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Extensive Cell Library

The UT0.25μCRH family of gate arrays is supported by an extensive cell library that includes SSI, MSI, and 54XX-equivalent functions, as well as RAM and other library functions. Userselectable options for cell configurations include scan for all register elements, as well as output drive strength. Aeroflex UTMC’s core library includes the following functions:

Intel® 80C31 equivalent

Intel® 80C196 equivalent

MIL-STD-1553 functions (BCRTM, RTI, RTMP)

MIL-STD-1750 microprocessor

Standard microprocessor peripheral functions

Configurable RAM (SRAM, DPsRAM)

RISC Microcontroller

USART (82C51)

EDAC

Refer to Aeroflex UTMC’s UT0.25μCRH Design Manual for complete cell listing and details.

I/O Buffers

The UT0.25μCRH gate array family offers up to 530 signal I/ O locations (note: device signal I/O availability is affected by package selection and pinout.) The I/O cells can be configured by the user to serve as input, output, bidirectional, three-state, or additional power and ground pads. Output drive options range from 2 to 12mA. To drive larger off-chip loads, output drivers may be combined in parallel to provide additional drive up to 24mA.

Other I/O buffer features and options include:

Pull-up and pull-down resistors

Schmitt trigger

LVDS

PCI

Cold Sparing

JTAG Boundary-Scan

The UT0.25μCRH arrays provide for a test access port and boundary-scan that conforms to the IEEE Standard 1149.1 (JTAG). Some of the benefits of this capability are:

Easy test of complex assembled printed circuit boards

Gain access to and control of internal scan paths

Initiation of Built-In Self Test

Clock Driver Distribution

Aeroflex UTMC design tools provide methods for balanced clock distribution that maximize drive capability and minimize relative clock skew between clocked devices.

Speed and Performance

Aeroflex UTMC specializes in high-performance circuits designed to operate in harsh military and radiation environments. Table 3 presents a sampling of typical cell delays.

Note that the propagation delay for a CMOS device is a function of its fanout loading, input slew, supply voltage, operating temperature, and processing radiation tolerance. In a radiation environment, additional performance variances must be considered. The UT0.25μCRH array family simulation models account for all of these effects to accurately determine circuit performance for its particular set of use conditions.

Power Dissipation

Each internal gate or I/O driver has an average power consumption based on its switching frequency and capacitive loading. Radiation-tolerant processes exhibit power dissipation that is typical of CMOS processes. For a rigorous power estimating methodology, refer to the Aeroflex UTMC UT0.25μCRH Design Manual or consult with a Aeroflex UTMC Applications Engineer.

Typical Power Dissipation

0.04μW/Gate-MHz@2.5V 20% duty cycle

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UTMC UT0.25uCRH Datasheet

 

Table 3. Typical Cell Delays

 

 

 

CELL

 

OUTPUT

 

PROPAGATION

 

 

 

 

TRANSITION

 

DELAY

1

 

 

 

 

 

Internal Gates

 

 

 

VDD = 2.5V

 

 

 

INV1, Inverter

 

HL

 

.068

 

 

 

 

 

 

LH

 

.090

 

INV4, Inverter 4X

 

HL

 

.035

 

 

 

LH

 

.050

 

NAND2, 2-Input NAND

 

HL

 

.102

 

 

 

LH

 

.103

 

NOR2, 2-Input NOR

 

HL

 

.080

 

 

 

LH

 

.148

 

DFF - CLK to Q

 

HL

 

.391

 

 

 

LH

 

.394

 

LDL - CLK to Q

 

HL

 

.474

 

 

 

LH

 

.352

 

Output Buffers

 

 

 

 

 

 

 

 

 

 

OC3325N4_C, CMOS

 

HL

 

4.599

 

 

 

 

 

 

LH

 

6.578

 

OC3325N12_C, CMOS

 

HL

 

3.060

 

 

 

LH

 

3.758

 

Input Buffers

 

 

 

 

 

 

 

 

 

 

IC3325_C, CMOS

 

HL

 

.468

 

 

 

 

 

 

LH

 

.313

 

 

 

 

 

 

 

Note:

1. All specifications in ns (typical). Output load capacitance is 50pF. Fanout loading for input buffers and gates is the equivalent of two gate input loads.

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