UTMC 5962R9475408VYX, 5962R9475408VYA, 5962R9475408VXX, 5962R9475408VXC, 5962R9475408QYX Datasheet

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UTMC 5962R9475408VYX, 5962R9475408VYA, 5962R9475408VXX, 5962R9475408VXC, 5962R9475408QYX Datasheet

Standard Products

UT22VP10 Universal RADPALTM

Data Sheet

 

November 2000

FEATURES

 

q High speed Universal RADPAL

q Radiation-hardened process and design; total dose irradia-

- tPD: 15.5ns, 20ns, 25ns maximum

tion testing to MIL-STD-883, Method 1019

- fMAX1: 33MHz maximum external frequency

- Total dose: 1.0E6 rads(Si)

- Upset threshold 50 MeV-cm2/mg (min)

- Supported by industry-standard programmer

- Latchup immune(LET>109 MeV-cm2/mg)

- Amorphous silicon anti-fuse

q Asynchronous and synchronous RADPAL operation

q QML Q & V compliant

-Synchronous PRESET

-

Asynchronous RESET

q Packaging options:

 

 

- 24-pin 100-mil center DIP (0.300 x 1.2)

q Up to 22 input and 10 output drivers may be configured

-

24-lead flatpack (.45 x .64)

-

CMOS & TTL-compatible input and output levels

-

28-lead quad-flatpack (.45 x .45)

-Three-state output drivers

q Standard Military Drawing 5962-94754 available

qVariable product terms, 8 to 16 per output

q10 user-programmable output macrocells

-Registered or combinatorial operation

-Output driver polarity control selectable

-Two feedback paths available

 

13

12

11

10

9

8

7

6

5

4

3

2

1

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

PROGRAMMABLE ARRAY LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

(132 X 44)

 

 

 

 

 

 

8

 

10

 

12

14

 

16

16

 

14

 

12

10

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preset

Macrocell

Macrocell

Macrocell

Macrocell

 

Macrocell

Macrocell

 

Macrocell

 

Macrocell

Macrocell

Macrocell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

14

 

15

16

 

17

 

18

19

 

20

 

21

22

23

24

Figure 1. Block Diagram

1

PRODUCT DESCRIPTION

The UT22VP10 RADPAL is a fuse programmable logic array device. The familiar sum-of-products (AND-OR) logic structure is complemented with a programmable macrocell. The UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and 28-lead quad-flatpack package offerings providing up to 22 inputs and 10 outputs. Amorphous silicon anti-fuse technology provides the programming of each output. The user specifies whether each of the potential outputs is registered or combinatorial. Output polarity is also individually selected, allowing for greater flexibility for output configuration. A unique output enable function allows the user to configure bidirectional I/O on an individual basis.

The UT22VP10 architecture implements variable sum terms providing 8 to 16 product terms to outputs. This feature provides the user with increased logic function flexibility. Other features include common synchronous preset and asynchronous reset. These features eliminate the need for performing the initialization function.

The UT22VP10 provides a device with the flexibility to implement logic functions in the 500 to 800 gate complexity. The flexible architecture supports the implementation of logic functions requiring up to 21 inputs and only a single output or down to 12 inputs and 10 outputs. Development and programming support for the UT22VP10 is provided by DATA I/O.

DIP & FLATPACK PIN CONFIGURATION

 

 

1

24

 

 

CK/I

 

 

VDD

2

23

 

I

 

I/O0

 

 

 

 

 

3

22

 

 

I

 

I/O1

 

 

 

 

 

4

21

 

 

I

 

I/O2

 

 

 

 

 

5

20

 

 

I

 

I/O3

6

19

 

 

 

 

 

I

 

I/O4

 

 

 

 

 

7

18

 

 

I

 

I/O5

 

 

 

 

 

8

17

 

 

I

 

I/O6

 

 

 

 

 

9

16

 

 

I

 

I/O7

10

15

 

 

 

 

 

I

 

I/O8

 

 

 

 

 

11

14

 

 

I

 

I/O9

 

 

 

VSS

 

12

13

 

I

 

 

QUAD-FLATPACK PIN CONFIGURATION

 

I

I

CK/I VDD VDD I/O0 I/O1

 

 

4

3

2

1

28

27

26

 

I

5

 

 

 

 

 

25

I/O2

 

 

 

 

 

 

I

6

 

 

 

 

 

24

I/O3

 

 

 

 

 

 

I

7

 

 

 

 

 

23

I/O4

 

 

 

 

 

 

VSS

8

 

 

 

 

 

22

VSS

 

 

 

 

 

 

I

9

 

 

 

 

 

21

I/O5

 

 

 

 

 

 

I

10

 

 

 

 

 

20

I/O6

 

 

 

 

 

 

I

11

 

 

 

 

 

19

I/O7

 

 

 

 

 

 

 

12

13

14

15

16

17

18

 

 

I

I

VSS

VSS

I

I/O9

I/O8

 

PIN NAMES

CK/I

Clock/Data Input

 

 

I

Data Input

 

 

I/O

Data Input/Output

 

 

VDD

Power

VSS

Ground

FUNCTION DESCRIPTION

The UT22VP10 RADPAL implements logic functions as sum- of-products expressions in a one-time programmable-AND/ fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility.

2

Table 1. Macrocell Configuration Table1, 2, 3

C2

C1

C0

Output Type

Polarity

Feedback

0

0

0

Registered

Active LOW

Registered

 

 

 

 

 

 

0

0

1

Registered

Active HIGH

Registered

 

 

 

 

 

 

X

1

0

Combinatorial

Active LOW

I/O

 

 

 

 

 

 

X

1

1

Combinatorial

Active HIGH

I/O

 

 

 

 

 

 

1

0

0

Registered

Active LOW

I/O

 

 

 

 

 

 

1

0

1

Registered

Active HIGH

I/O

 

 

 

 

 

 

Notes:

1.0 equals programmed low or programmed.

2.1 equals programmed high or unprogrammed.

3.X equals don’t care.

OVERVIEW

The UT22VP10 RADPAL architecture (see figure 1) has 12 dedicated inputs and 10 I/Os to provide up to 22 inputs and 10 outputs for creating logic functions. At the core of the device is a one-time programmable anti-fuse AND array that drives a fixed OR array. With this structure, the UT22VP10 can implement up to 10 sum-of-products logic expressions.

Associated with each of the 10 OR functions is a macrocell which is independently programmed to one of six different configurations. The one-time programmable macro cells allow each I/O to create sequential or combinatorial logic functions with either Active-High or Active-Low polarity.

LOGIC ARRAY

The one-time programmable AND array of the UT22VP10 RADPAL is formed by input lines intersecting product terms. The input lines and product terms are used as follows:

44 input lines:

24 input lines carry the true and complement of the signals applied to the input pins

20 lines carry the true and complement values of feedback or input signals from the 10 I/Os

132 product terms:

120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logic sums

10 output enable terms (one for each I/O)

1 global synchronous preset term

1 global asynchronous reset term

At each input-line/product-term intersection there is an antifuse cell which determines whether or not there is a logical connection at that intersection. A product term which is connected to both the true and complement of an input signal will always be logical zero, and thus will not effect the OR function that it drives. When there are no connections on a product term

a Don’t Care state exists and that term will always be a logical one.

PRODUCT TERMS

The UT22VP10 provides 120 product terms that drive the 10 OR functions. The 120 product terms connect to the outputs in two groups of 8, 10, 12, 14, and 16 to form logical sums.

MACROCELL ARCHITECTURE

The output macrocell provides complete control over the architecture of each output. Configuring each output independently permits users to tailor the configuration of the UT22VP10 to meet design requirements.

Each I/O macrocell (see figure 2) consists of a D flip-flop and two signal-select multiplexers. Three configuration select bits controlling the multiplexers determine the configuration of each UT22VP10 macrocell (see table 1). The configuration select bits determine output polarity, output type (registered or combinatorial) and input feedback type (registered or I/O). See figure 3 for equivalent circuits for the macrocell configurations.

OUTPUT FUNCTIONS

The signal from the OR array may be fed directly to the output pin (combinatorial function) or latched in the D flip-flop (registered function). The D flip-flop latches data on the rising edge of the clock. When the synchronous preset term is satisfied, the Q output of the D flip-flop output will be set logical one at the next rising edge of the clock input. Satisfying the asynchronous clear term sets Q logical zero, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset.

3

AR

OUTPUT

SELECT

 

 

 

 

MUX

D

Q

 

 

CK

Q

C1

C0

 

 

SP

 

 

INPUT/

 

 

FEEDBACK

 

 

 

MUX

 

 

C1

C2

 

 

C1

 

 

 

C0

 

 

 

C2

 

Figure 2. Macrocell

 

 

 

 

OUTPUT POLARITY

Each macrocell can be configured to implement Active-High or Active-Low logic. Programmable polarity eliminates the need for external inverters.

OUTPUT ENABLE

The output of each I/O macrocell can be enabled or disabled under the control a programmable output enable product term. The output signal is propagated to the I/O pin when the logical conditions programmed on the output enable term are satisfied. Otherwise, the output buffer is driven to the high-impedance state.

The output enable term allows the I/O pin to function as a dedicated input, dedicated output, or bidirectional I/O. When every connection is unprogrammed, the output enable product term permanently enables the output buffer and yields a dedicated output. If every connection is programmed, the enable term is logically low and the I/O functions as a dedicated input.

REGISTER FEEDBACK

The feedback signal to the AND array is taken from the Q output when the I/O macrocell implements a registered function

(C2 = 0, C1 = 0).

BIDIRECTIONAL I/O

The feedback signal is taken from the I/O pin when the macrocell implements a combinatorial function (C1 = 1) or a registered function (C2 = 1, C1 = 0). In this case, the pin can be used as a dedicated input, a dedicated output, or a bidirectional I/O.

POWER-ON RESET

To ease system initialization, all D flip-flops will power-up to a reset condition and the Q output will be low. The actual output of the UT22VP10 will depend on the programmed output polarity. The reset delay time is 5μs maximum. See the Power-up Reset section for a more descriptive list of POR requirements.

ANTI-FUSE SECURITY

The UT22VP10 provides a security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer at the conclusion of the programming cycle. Once the security bit is set it is no longer possible to verify (read) or program the UT22VP10. NOTE: UTMC does not recommend using the

UT22VP10 unless the security fuse has been programmed. The security bit must be blown to ensure proper functionality of the UT22VP10.

4

AR

D Q

CK Q

SP

Registered Feedback, Registered, Active-Low Output (C2 = 0, C1 = 0, C0 = 0)

AR

D Q

CK Q

SP

Registered Feedback, Registered, Active-High Output (C2 = 0, C1 = 0, C0 = 1)

I/O Feedback, Combinatorial, Active-Low Output (C2 = X, C1 = 1, C0 = 0)

Figure 3. Macrocell Configuration (continued on next page)

5

I/O Feedback, Combinatorial, Active-High Output (C2 = X, C1 = 1, C0 = 1)

AR

D Q

CK Q

SP

I/O Feedback, Registered, Active-Low Output (C2 = 1, C1 = 0, C0 = 0)

AR

D Q

CK Q

SP

I/O Feedback, Registered, Active-High Output (C2 = 1, C1 = 0, C0 = 1) Figure 3. Macrocell Configuration

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