UTMC 5962R-0323502VUX, 5962R-0323502VUC, 5962R-0323502VUA, 5962R-0323502QUC, 5962R-0323502QUA Datasheet

1

IN DEVELOP

M

E

NT

MEMORY

ARRAY

COLUMN

I/O

INPUT

DRIVERS

INPUT

DRIVERS

ROW

DECODER

OUTPUT ENABLE

E2

W

G

E1

CHIP ENABLE

OUTPUT

DRIVERS

DATA

WRITE

CIRCUIT

DATA
READ

CIRCUIT

COLUMN

DECODER

WRITE ENABLE

INPUT

DRIVERS

INPUT

DRIVERS

TOP/BOTTOM

DECODER

BLOCK

DECODER

INPUT

DRIVERS

A(18:0)

INPUT

DRIVER

DQ(7:0)

Figure 1. UT8R512K8 SRAM Block Diagram

FEATURES

q 15ns maximum access time
q Asynchronous operation for compatibility with industry-

standard 512K x 8 SRAMs

q CMOS compatible inputs and output levels, three-state

bidirectional data bus

- I/O Voltage 3.3 volts, 1.8 volt core

q Radiation performance

- Intrinsic total-dose: 100K rad(Si)

- SEL Immune >100 MeV-cm2/mg

- Onset LET > TBD

- Memory Cell Saturated Cross Section TBD

- Neutron Fluence: 3.0E14n/cm

2

- Dose Rate

- Upset 1.0E9 rad(Si)/sec

- Latchup >1.0E11 rad(Si)/sec

q Packaging options:

- 36-lead ceramic flatpack

q Standard Microcircuit Drawing 5962-03235

- QML compliant part

INTRODUCTION

The UT8R512K8 is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.

Writing to the device is accomplished by taking chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the eight I/O pins (DQ0 through DQ7)
is then written into the location specified on the address pins
(A0 through A18). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.

The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected ( E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation ( E1 LOW, E2 HIGH and W LOW).

Standard Products

UT8R512K8 512K x 8 SRAM

Advanced Data Sheet

April 11, 2003

2

IN DEVELOP

M

E

NT

PIN NAMES

DEVICE OPERATION

The UT8R512K8 has four control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), and Output Enable ( G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). E1 and E2 device enables control device selection,
active, and standby modes. Asserting E1 and E2 enables the
device, causes I

DD

to rise to its active value, and decodes the 19

address inputs to select one of 524,288 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of W and E2 greater than V

IH

(min) and E1 less

than V

IL

(max) defines a read cycle. Read access time is

measured from the latter of device enable, output enable, or valid
address to valid data output.

SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t

AVQV

is satisfied. Outputs

remain active throughout the entire cycle. As long as device
enable and output enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t

AVAV

).

SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by E1 and E2 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified t

ETQV

is satisfied, the

eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).

SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is t

GLQV

unless t

AVQV

or t

ETQV

have not been

satisfied.

A(18:0) Address W WriteEnable

DQ(7:0) Data Input/Output G Output Enable

E1 Enable V

DD1

Power (1.8V)

E2 Enable V

DD2

Power (3.3V)

V

SS

Ground

1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19

Figure 2. 15ns SRAM Pinout (36)

E2
A18
A17
A16
A15
G
DQ7
DQ6
V

SS

V

DD1

DQ5
DQ4
A14
A13
A12
A11
A10
V

DD2

A0
A1
A2
A3
A4

E1
DQ0
DQ1

V

DD1

V

SS

DQ2
DQ3

W
A5
A6
A7
A8
A9

G W E2 E1 I/O Mode Mode
X X X 1 3-state Standby
X X 0 X 3-state Standby
X 0 1 0 Data in Write

1 1 1 0 3-state

Read

2

0 1 1 0 Data out Read

3

IN DE

VE

L

O

PMENT

WRITE CYCLE

A combination of W and E1 less than VIL(max) and E2
greater than VIH(min) defines a write cycle. The state of G is
a “don’t care” for a write cycle. The outputs are placed in the

high-impedance state when either G is greater than VIH(min),
or when W is less than VIL(max).

Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by
t

WLWH

when the write is initiated by W, and by t

ETWH

when

the write is initiated by E1 or E2. Unless the outputs have
been previously placed in the high-impedance state by G, the
user must wait t

WLQZ

before applying data to the nine

bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure

4b, is defined by a write terminated by the latter of E1 or E2
going inactive. The write pulse width is defined by t

WLEF

when the write is initiated by W, and by t

ETEF

when the write

is initiated by either E1or E2 going active. For the W initiated
write, unless the outputs have been previously placed in the
high-impedance state by G, the user must wait t

WLQZ

before

applying data to the eight bidirectional pins DQ(7:0) to avoid
bus contention.

RADIATION HARDNESS

The UT8R512K8 SRAM incorporates special design and
layout features which allows operation in a limited radiation
environment.

Table 2. Radiation Hardness

Design Specifications

1

Notes:

1. The SRAM is immune to latchup.

2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils
of Aluminum.

Supply Sequencing

No supply voltage sequencing is required between V

DD1

and

V

DD2

.

Total Dose 100K rad(Si)

Heavy Ion
Error Rate

2

TBD Errors/Bit-Day

4

I

N DE

VELOPMENT

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD1

DC supply voltage -0.3 to 2.0V

V

DD2

DC supply voltage -0.3 to 3.8V

V

I/O

Voltage on any pin -0.3 to 3.8V

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 1.2W

T

J Maximum junction temperature

2

+150°C

Θ

JC Thermal resistance, junction-to-case

3

5°C/W

I

I

DC input current

±5 mA

SYMBOL PARAMETER LIMITS

V

DD1

Positive supply voltage 1.7 to 1.9V

V

DD2

Positive supply voltage 3.0 to 3.6V

T

C

Case temperature range (C) Screening: -55 to +125°C

(W) Screening: -40 to +125 °C

V

IN

DC input voltage 0V to V

DD2

I

N

D

EVE

L

OP

M

E

NT

5

DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*

(-55°C to +125°C for (C) screening and -40°C to 125°C for (W) screening)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

4. VIH = V

DD2

(max), VIL = 0V.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IH

High-level input voltage .7*V

DD2

V

V

IL

Low-level input voltage .3*V

DD2

V

V

OL1

Low-level output voltage IOL = 8mA,V

DD2

=V

DD2

(min) .2*V

DD2

V

V

OH1

High-level output voltage IOH = -4mA,V

DD2

=V

DD2

(min) .8*V

DD2

V

C

IN

1

Input capacitance ƒ = 1MHz @ 0V 12 pF

C

IO

1

Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF

I

IN

Input leakage current VIN = V

DD2

and V

SS

-2 2 µA

I

OZ

Three-state output leakage
current

VO = V

DD2

and V

SS, VDD2

= V

DD2

(max)

G = V

DD2

(max)

-2 2 µA

I

OS

2, 3

Short-circuit output current V

DD2

= V

DD2

(max), VO = V

DD2

V

DD2

= V

DD2

(max), VO = V

SS

-100 +100 mA

I

DD1

(OP1) Supply current operating

@ 1MHz

Inputs : VIL = VSS + 0.2V
VIH = V

DD2

- 0.2V, I

OUT

= 0

V

DD1

= V

DD1

(max), V

DD2

= V

DD2

(max)

15 mA

I

DD1

(OP2) Supply current operating

@66MHz

Inputs : VIL = VSS + 0.2V,
VIH = V

DD2

- 0.2V, I

OUT

= 0

V

DD1

= V

DD1

(max), V

DD2

= V

DD2

(max)

85 mA

I

DD2

(OP1) Supply current operating

@ 1MHz

Inputs : VIL = VSS + 0.2V
VIH = V

DD2

- 0.2V, I

OUT

= 0

V

DD1

= V

DD1

(max), V

DD2

= V

DD2

(max)

1 mA

I

DD2

(OP2) Supply current operating

@66MHz

Inputs : VIL = VSS + 0.2V,
VIH = V

DD2

- 0.2V, I

OUT

= 0

V

DD1

= V

DD1

(max), V

DD2

= V

DD2

(max)

12 mA

IDD(SB)

4

Total combined current
standby

A(18:0) static (0Hz)

CMOS inputs , I

OUT

= 0

E1 = V

DD2

- 0.2, E2 = GND

V

DD1

= V

DD1

(max), V

DD2

= V

DD2

(max)

15 mA

IDD(SB)

4

Total combined current
standby

A(18:0) @ 66MHz

CMOS inputs , I

OUT

= 0

E1 = V

DD2

- 0.2, E2 = GND,

V

DD1

= V

DD1

(max), V

DD2

= V

DD2

(max)

15 mA